Static information storage and retrieval – Read/write circuit – Having particular data buffer or latch
Reexamination Certificate
2002-10-30
2004-03-02
Lebentritt, Michael S. (Department: 2824)
Static information storage and retrieval
Read/write circuit
Having particular data buffer or latch
C365S154000, C365S189020, C365S198000, C365S230030, C365S230080
Reexamination Certificate
active
06700823
ABSTRACT:
BACKGROUND
1. Technical Field
The present invention relates generally to electrical circuits and, more particularly, to input/output circuits.
2. Related Art
High-speed differential signaling offers many advantages, such as low noise and low power while providing a robust and high-speed data transmission. Differential signaling differs from other types of signaling methods in that, instead of designating a precise voltage level for a logical one or a logical zero, differential signaling specifies a voltage differential (e.g., a positive or a negative voltage drop across a resistive load). One type of high-speed differential signaling is referred to as low voltage differential signaling (LVDS), which exists in many different forms (e.g., such as described in IEEE standard 1596.3 and HyperTransport specifications) due to its deployment across market segments for numerous applications.
Typically, high-speed differential input/output circuits (also referred to as input/output buffers, receiver/transmitter circuits, or receiver/driver circuits) require differential mode termination (e.g., the resistive load) to match the differential impedance of the transmission medium (or channel). The transmission medium (e.g., printed-circuit board traces, backplanes, a differential wire pair, or cables) couples the output circuit to the input circuit and provides a path along which the intended information travels.
Because the receivers only respond to differential voltages, common mode modulations are generally rejected by the receivers. However, common mode signals may pose certain problems with differential signaling systems. For example, the common mode signals, if not terminated, may consume a large portion of a receiver's finite common mode voltage range or, if the common mode signal is driven into resonance, exceed the common mode range of the receiver. Furthermore, a certain portion of the common mode signal may also be transformed into a differential signal due to, for example, inequalities in line impedance or loading of the transmission channel. Consequently, common mode signals may interfere with or degrade the communication of the desired information. As a result, it is desirable to provide systems and methods for providing a common mode termination near the input circuits or output circuits to dampen or terminate common mode signals.
BRIEF SUMMARY
Systems and methods are disclosed herein to provide a common mode termination for input/output circuits. For example, in accordance with an embodiment of the present invention, a common mode termination is provided for each input circuit and each output circuit within a bank of input/output circuits (i.e., a number of input/output circuits). The common mode termination may be programmable to couple a common mode terminal for each input/output circuit to ground using an off-chip capacitor or an on-chip capacitor. The common mode termination for each input circuit and each output circuit may be programmably coupled through a corresponding common bus. Furthermore, each common bus may be designed to function as on-chip capacitance.
More specifically, in accordance with one embodiment of the present invention, an input/output circuit bank includes a plurality of input circuits each having input leads adapted to couple to a corresponding transmission channel; a plurality of output circuits, with each of the output circuits coupled to the input leads of a corresponding one of the input circuits to share the transmission channel; a plurality of resistor pairs, each of the resistor pairs coupled across the input leads of a corresponding one of the input circuits; a common mode node coupled to each of the resistor pairs; and a bus coupled to the common mode nodes and adapted to provide a common mode termination for the input circuits.
In accordance with another embodiment of the present invention, a method of providing a common mode termination for a bank of input/output circuits includes providing a load across input leads of each of the input circuits within the bank; inserting a common mode node between the input leads of each of the input circuits within the bank; and coupling the common mode node for each of the input circuits to a bus which provides a common mode termination path for common mode signals associated with the input circuits.
REFERENCES:
patent: 5631866 (1997-05-01), Oka et al.
patent: 5917758 (1999-06-01), Keeth
patent: 6577164 (2003-06-01), Tomita
Hirad Samavati et al., “Fractal Capacitor” IEEE Journal of Solid-State Circuits, vol. 33, No. 12, Dec. 1998, pp. 2035-2041.
Andrea Boni et al., “LVDSI I/O Interface for Gb/s-per-Pin Operation in 0.35&mgr;m CMOS”, IEEE Journal of Solid-State Circuits, vol. 36, No. 4, Apr. 2001, pp. 706-711.
Rahman Arifur
Scholz Harold
Chen & Heid LLP
Kwok MacPherson
Lattice Semiconductor Corporation
Lebentritt Michael S.
Luu Pho M.
LandOfFree
Programmable common mode termination for input/output circuits does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Programmable common mode termination for input/output circuits, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Programmable common mode termination for input/output circuits will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3221771