Electrical computers and digital processing systems: support – Synchronization of clock or timing signals – data – or pulses
Reexamination Certificate
2007-05-15
2007-05-15
Trujillo, James K. (Department: 2116)
Electrical computers and digital processing systems: support
Synchronization of clock or timing signals, data, or pulses
C713S401000, C713S500000, C713S600000, C713S601000
Reexamination Certificate
active
10630159
ABSTRACT:
A programmable synchronizer system for effectuating data transfer across a clock boundary between a core clock domain and a bus clock domain, wherein the core clock domain is operable with a core clock signal and the bus clock domain is operable with a bus clock signal, the core and bus clock signals having a ratio of N core clock cycles to M bus clock cycles, where N/M≧1. A first synchronizer is provided for synchronizing data transfer from a core clock domain logic block to a bus clock domain logic block. A second synchronizer is operable to synchronize data transfer from the bus clock domain logic block to the core clock domain logic block. Control means are included for controlling the first and second synchronizers, the control means operating responsive at least in part to configuration means that is configurable based on skew tolerance and latency parameters.
REFERENCES:
patent: 5256912 (1993-10-01), Rios
patent: 5347559 (1994-09-01), Hawkins et al.
patent: 5434996 (1995-07-01), Bell
patent: 5721886 (1998-02-01), Miller
patent: 5884100 (1999-03-01), Normoyle et al.
patent: 6075832 (2000-06-01), Geannopoulos et al.
patent: 6084934 (2000-07-01), Garcia et al.
patent: 6114915 (2000-09-01), Huang et al.
patent: 6134155 (2000-10-01), Wen
patent: 6175603 (2001-01-01), Chapman et al.
patent: 6246275 (2001-06-01), Wodnicki et al.
patent: 6249875 (2001-06-01), Warren
patent: 6326824 (2001-12-01), Hosoe et al.
patent: 6369624 (2002-04-01), Wang et al.
patent: 6516362 (2003-02-01), Magro et al.
patent: 6529083 (2003-03-01), Fujita
patent: 6633994 (2003-10-01), Hofmann et al.
patent: 2002/0051509 (2002-05-01), Lindner et al.
patent: 2002/0158671 (2002-10-01), Wang et al.
patent: 2002/0196886 (2002-12-01), Adkisson
patent: 2002/0199124 (2002-12-01), Adkisson
Search Report under Section 17 in GB0409008.0 from the UK Patent Office (date of search Aug. 19, 2004), 1 page.
Hewlett--Packard Development Company, L.P.
Trujillo James K.
LandOfFree
Programmable clock synchronizer does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Programmable clock synchronizer, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Programmable clock synchronizer will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3767777