Programmable and stable threshold CMOS inverter

Details Programmable and stable threshold CMOS inverter Programmable and stable threshold CMOS inverter

1994-09-14

1996-02-20

Westin, Edward P.

Electronic digital logic circuitry

Signal sensitivity or transmission integrity

Signal level or switching threshold stabilization

326 58, H03K 190948

Patent

active

054932351

ABSTRACT:
An inverter circuit having a readily programmable and stable threshold voltage and low propagation delay. An input stage of the inverter includes a pair of transistors, a first one adapted to receive an input signal for inversion and being disposed in a first current path and a second one being disposed in a second current path. The input stage further comprises a third transistor connected in series with the first transistor and receiving a bias voltage. The first, second, and third transistors are all of the same type; i.e., all NMOS or all PMOS. An output stage of the inverter includes a PMOS transistor and an NMOS transistor having interconnected drain terminals at which an inverted output signal is provided. The threshold voltage about which the output signal transitions is a function of the bias voltage and characteristics of the first, second, and third transistors in the input stage.

REFERENCES:
patent: 4042839 (1977-08-01), Araki
patent: 4714840 (1987-12-01), Proebsting
patent: 4808852 (1989-02-01), Kousaka et al.
patent: 5045721 (1991-09-01), Yan
patent: 5124580 (1992-06-01), Matthews et al.
patent: 5172016 (1992-12-01), Dobberpuhl
Klass Bult and Hans Wallinga, "A Class of Analog CMOS Circuits Based on the Square-Law Characteristic of an MOS Transistor in Saturation", IEEE Journal of Solid-State Circuits, vol. SC-22, Jun. 1987, pp. 357-365.

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