Program optimizing circuit and method for an electrically erasab

Details Program optimizing circuit and method for an electrically erasab Program optimizing circuit and method for an electrically erasab

1991-04-08

1993-04-20

LaRoche, Eugene R.

Static information storage and retrieval

Read/write circuit

Accelerating charge or discharge

365 96, G11C 700

Patent

active

052048390

ABSTRACT:
A program optimizing circuit for an EEPROM array comprising a program voltage generating circuit connected to each of bit lines, an anti-program voltage generating circuit connected between input/output data line and data input/output buffer and circuit for causing column decoder to selectively produce anti-program voltage or column address, is disclosed. The program voltage generating circuit further includes a first high voltage pumping circuit, transfer means and latch circuit. The operation of the first high voltage pumping circuit is controlled by the data stored in the latch circuit. In programming, the anti-program voltage is applied to all the bit lines, so as to prevent the unwanted memory cells from being programmed or erased.

REFERENCES:
patent: 4423492 (1983-12-01), Yoshida
patent: 4918663 (1990-04-01), Remington
patent: 5103425 (1992-04-01), Kuo

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