Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2002-02-21
2004-10-26
Booth, Richard A. (Department: 2812)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S278000
Reexamination Certificate
active
06808985
ABSTRACT:
BACKGROUND OF THE INVENTION
(1) Field of the Invention
The present invention relates to semiconductor manufacturing and is more particularly directed to expeditious conversion of embedded flash/EEPROM (electrically erasable programmable read only memory) products into other novel memory products.
(2) Description of the Related Art
In the manufacture of ROM products, it is usually the practice in the present manufacturing line to stock partially completed memory parts in a wafer bank and then finish them after having received a customer ordered ROM code, as will be explained more later. Then the completed wafer is assembled and tested before the product is shipped to the customer. Important factors in running a memory manufacturing line include turn-around-time (TAT), time to market and cost that are associated with the making of the product.
Digital memories allow for data storage (or writing) as well as data retrieval (or reading). Memories in which both of these functions can be rapidly and easily performed, and whose cells can be accessed in random order, are referred to as random-access memories (RAMs). Read-only memories (ROMs) are those in which only the read operation can be performed rapidly. As is known, entering data into a ROM, however, is referred to as programming the ROM, to emphasize that this operation is much slower than the writing operation used in RAMs.
In semiconductor RAMs, information is stored on each cell either through the charging of a capacitor or the setting of the state of a bistable flip-flop circuit. With either method, the information on the cell is destroyed if the power is interrupted. Such memories are therefore referred to as volatile memories. When charge on a capacitor is used to store data in a semiconductor-RAM cell, the charge needs to be periodically refreshed, since leakage currents will remove it in a few milliseconds. Hence, volatile memories based on this storage mechanism are known as dynamic RAMs, or DRAMs.
If the data is stored (i.e., written into the memory) by setting the state of a flip-flop, it will be retained as long as power is connected to the cell (and no other write signals are received). As is known in the art, RAMs fabricated with such cells are called static RAMs, or SRAMS.
It is often desirable to use memory devices that will retain information even when the power is temporarily interrupted (or when the device is left without applied power for indefinite periods). Magnetic media offer such nonvolatile-memory storage In addition, a variety of semiconductor memories have been developed with this characteristic. At present, virtually all such nonvolatile memories are ROMs. While data can be entered into these memories, the programming procedure varies from one type of ROM to the other.
The first group of nonvolatile memories consists of those ROMs in which data is entered during manufacturing, and cannot subsequently be altered by the user. These devices are known as masked ROMs (or simply ROMs). The next category consists of memories whose data can be entered by the user (user-programmable ROMs). In the first example of this type, known as a programmable ROM, or PROM, data can be entered into the device only once.
In the remaining ROM types, data can be erased as well as entered. In one class of erasable ROMs, the cells must be exposed to a strong ultraviolet light in order for stored data to be erased. These ROMs are called erasable-programmable ROMs, or EPROMs. In the final type, data can be electrically erased as well as entered into the device; these are well-known as EEPROMs. The time needed to enter data into both EPROMs and EEPROMs is much longer than the time required for the write operation in a RAM.
The most cost effective, high volume production non-volatile memory used principally for program or instruction storage is the mask programmable Read Only Memory (ROM). The mask programmable ROM is dense, offers high access speed, and requires no special processing steps when used in standard MOS logic processes. However, while in development stages of the ROM code for these products, they often need to be re-programmed, which requires generation of a mask and the processing of at least a few wafers for code verification. The re-programming can be quite costly. Furthermore, the poor TAT can result in high chip development cost and costly “time to market” delays. Given the program complexity of today's micro-controllers and DSPs, repeated changes to program code or software is common.
One solution that has been found in prior art is the use of emulator chips. These chips remove the ROM and port the ROM addresses, control, and data I/O to chip pins for interface to an external Programmable Read Only Memory or PROM. Another method that may be used for code development is based on fuse or anti-fuse technology. Because of a reduced current requirement for programming the cell, anti-fuse technology has been preferred over fuse technology for MOS based memories. Anti-fuse technology uses an insulating element in the contact of an addressable cell which can be shorted by passing a relatively high voltage and current through the insulating element thereby causing a rupture or short and thus, a state change from an insulating element to a conductive element. Insulators include oxide (SiO
2
), silicon nitride (Si
3
N
4
), various combinations of oxides and nitrides, polysilicon, and amorphous silicon. These types of memories are used in permanent applications requiring reliability and, therefore, need special high voltage transistors to program the cells. The addition of these special transistors to the process adds to its cost and are not required.
Worley, in U.S. Pat. No. 6,021,079 discloses an anti-fuse PROM which is embedded into a conventional CMOS process with some additional process steps and additional area for the wire circuitry. Nominal, low voltage transistors are used to program the PROM such that these transistors remain functional some time after programming for the purposes of verifying functionality of the memory's programming code. Once the program code has been verified a low cost production version of the part then can be made using standard ROM mask programming.
Another known programming method is called oxide programming which provides for two types of metal oxide semiconductor field effect transistors (MOSFET) by the use of different gate oxide layer thickness for each transistor type. Each oxide layer thickness corresponds to a different transistor threshold voltage. In programmed cells, the thickness of the gate oxide layer is about the same thickness as the field oxide, thereby providing a transistor which is permanently “off” or in a logic “0” state. Unprogrammed cells include typical thicknesses for the gate oxide layer so that the transistor is “on” or in logic “1” state. A disadvantage of the field oxide programming method includes a longer product TAT as measured from the programming step. Much of the process occurs after programming the gate oxide layers of the cells. Huang, et al., in U.S. Pat. No. 6,037,222 disclosed such a method for fabricating a dual-gate dielectric module for memory embedded logic using salicide technology and polycide technology.
On the other hand, You, et al., in U.S. Pat. No. 6,020,241 teach a threshold voltage implant method of manufacturing a ROM that is code implanted late in the process after the first level metal, thus reducing the TAT to ship a customer order. This method changes the transistor threshold voltage by ion implanting the transistor gates for programmed cells. In n-channel devices, impurities such as boron are implanted into exposed gates which raise their threshold voltage. The implant forces the gates of the cells permanently to an “off” state. Unexposed gates are not implanted and therefore provide cells at an “on” state. Heavy implants, however, often create damage to the thin gate oxide region. Damage to the gate oxide region causes higher parasitic junction capacitance between the source (or drain) and channel region of the metal o
Chen Jiun-Nan
Chih Yue-Der
Chou Shao-Yu
Chu Sam Sheng-Deh
Kuo Feng-Ming
Booth Richard A.
Taiwan Semiconductor Manufacturing Company
Thomas Kayden Horstemeyer & Risley
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