Production of a semiconductor device having a P-well

Details Production of a semiconductor device having a P-well Production of a semiconductor device having a P-well

2001-06-08

2002-03-26

Tsai, Jey (Department: 2812)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S306000, C438S199000, C438S981000

Reexamination Certificate

active

06362059

ABSTRACT:

FIELD OF THE INVENTION
This invention relates to a process for preparing a semiconductor device having a gate insulation film with plural different levels of thickness formed thereon and a N-channel region formed in the predetermined MOSFET region thereof using indium, in particular to the process for preparing a semiconductor device that is capable of implanting indium effectively.
BACKGROUND OF THE INVENTION
With the miniaturization of a MOSFET (Metal Oxide Semiconductor Field Effect Transistor), the necessity of forming super-micro devices of such sizes that are 0.1 &mgr;m or less arises. Accompanied by this event, how to restrain the deterioration of short channel properties such as forward and reverse short channel effects conspicuously appearing in proportion to the miniaturization is in problem. The reverse short channel effect appears resulting from the re-distribution of channel impurity concentration induced by diffusion. On account of this, as for a channel impurity in a NMOSFET, boron that has large re-distributed amount of impurities is being replaced by another element such as indium that has large atomic weight, small amount of diffusion and small re-distributed amount of impurities.
On the other hand, along with the miniaturization of the MOSFET, a SOC (System On a Chip) process for mounting various MOSFET's each having a gate insulation film of different thickness from each other such as MOSFET for use in a portion of a core region, MOSFET for low electric power use, MOSFET for use in a peripheral input/output circuit, high-density MOSFET for use in a high speed SRAM (Static Random Access Memory) on one semiconductor chip. In order to form a gate insulation film with different levels of thickness, techniques such as thermal oxidation using an oxidation furnace for forming a gate insulation film of a MOSFET for use in a portion of an I/O (Input/Output) region, RTP (Rapid Thermal Process) for forming a gate insulation film of a MOSFET for use in a portion of a core region are adopted. Here, RTP includes, for example, a process including the steps of annealing at predetermined temperature (e.g., 800° C.) for predetermined period of time (e.g., 1 minute) using NH
3
gas.
SUMMARY OF THE DISCLOSURE
However, there is much desired in the art. Namely indium has such a property that it is easy to be absorbed out of a channel region into the gate insulation film in case of forming a gate insulation film applying thermal oxidation. As a result, such a problem will occur that effects imparted by indium are lowered though indium ion implantation has been done with considerable effort.
An object of the present invention is to provide a process for preparing a semiconductor device which is capable of forming micro-devices of, e.g., 0.1 &mgr;m or less using indium and at the same time implanting indium effectively during the process of forming a gate insulation film with different levels of thickness.
In a first aspect of the present invention, a process is directed for preparing a semiconductor device having a gate insulation film with plural different levels of thickness formed on the semiconductor device and a N-channel region formed in the predetermined MOSFET region of the semiconductor device using indium, and includes (1) 1st step of forming a 1st resist mask on a predetermined region lying on a P-type silicon substrate having an element isolation region formed on the substrate to form a P-well region and thereafter forming a 1st N-channel region made of components other than indium on the P-well region, (2) 2nd step of removing the 1st resist mask and thereafter forming a 1st gate insulation film on the surface of the substrate, (3) 3rd step of forming a 2nd resist mask on the predetermined region except the 1st N-channel region after forming the 1st gate insulation film, and removing partially the 1st gate insulation film, (4) 4th step of forming a P-well region inside the 1st gate insulation film partially removed region and thereafter forming a 2nd N-channel region containing indium on this P-well region, and (5) 5th step of removing the 2nd resist mask and thereafter forming a 2nd gate insulation film on the surface of the 2nd N-channel region.
In the above process, it is preferable that the thickness of the 2nd gate insulation film is thinner than that of the 1st gate insulation film.
It is also preferable in the above process that the 2nd gate insulation film is formed by RTP.
In a second aspect of the present invention, a process is directed for preparing a semiconductor device having a gate insulation films with plural different levels of thickness formed on the semiconductor device and a N-channel region formed in the predetermined MOSFET region of the semiconductor device using indium, and includes (1) 1st step of forming a 1st resist mask on a predetermined region lying on a P-type silicon substrate having an element isolation region formed on the substrate to form a P-well region before forming a 1st N-channel region made of components other than indium on the P-well region, (2) 2nd step of removing the 1st resist mask before forming a 1st gate insulation film on the surface of the substrate, (3) 3rd step of forming a 2nd resist mask on the predetermined region except the 1st N-channel region after forming the gate insulation film, thereafter, forming a P-well region in the predetermined region except the 1st N-channel region through the gate insulation film before forming a 2nd N-channel region containing indium on this P-well region; and (4) 4th step of removing thinly the surface of the gate insulation film formed on the 2nd N-channel region.
It is preferable with regard to the aforementioned processes that the thickness of the gate insulation film on the 2nd N-channel region is 20 Å or less.


REFERENCES:
patent: 5960319 (1999-09-01), Iwata et al.
patent: 6232244 (2001-05-01), Ibok

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