Electrical computers and digital processing systems: processing – Processing control – Specialized instruction processing in support of testing,...
Reexamination Certificate
2000-07-25
2004-02-03
Coleman, Eric (Department: 2183)
Electrical computers and digital processing systems: processing
Processing control
Specialized instruction processing in support of testing,...
C714S045000
Reexamination Certificate
active
06687811
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention The present invention relates to a processor with an internal trace memory for storing access information on an internal bus.
2. Description of the Background Art
For a processing system operable on a software, such as a processor, debug (error detection and correction) operation such as verification of the software is carried out. In this debug operation, a cause for error generation is detected using the order of execution of instructions of the processor and data information accessed in the execution of the instructions. Collection of such information is generally called tracing of execution of a processor. With this trace information, an actual operating state of the processor can be monitored and a cause for error generation is detected with ease, which makes software debugging performed efficiently.
In order to trace execution of a processor, a trace memory is generally provided externally to a processor (chip), and bus access information such as an address, data and a bus control signal generated by the processor are stored in the trace memory provided externally to the processor and debugging of a software is executed using the stored information.
Storage of bus access information into the trace memory, however, is executed through a dedicated interface circuit or a general interface circuit provided in the processor. When an internal operating frequency of the processor is a high speed of, for example, 200 MHz or 300 MHz, this internal operating speed excels a frequency of the external bus significantly. The interface circuit is provided so as to buffer a difference in operating speed between the external bus and the inside of the processor. When bus access information such as internal data/signals is stored into the trace memory, transfer of the information is carried out at a low speed according to the operating frequency of the external bus. Therefore, the bus access information cannot be stored into the trace memory at the internal operating speed of the processor, so that only information of the internal bus access information, which has been thinned out selectively according to the operating frequency of the external bus, can be directly written into the trace memory.
In connection with such a high speed processor as well, there have been made proposals on configurations in, for example, Japanese Patent Laying-Open Nos. 2-310738 and 2-208785. A trace memory is incorporated in a processor in order to trace bus access information. In the configurations, after completion of tracing, bus access information is read out from the internal trace memory and debugging of a software or the like is executed.
In a case where a trace memory is incorporated in a processor as described above and such a processor is shipped as a product, the trace memory is delivered to a customer or the like staying within the processor. This trace memory is not used for actual data processing but exclusively for software debugging on the processor. Hence, there has arisen a problem of increase in cost of the processor since a chip area of this processor increases to accommodate the trace memory, which is used only in debugging of a program.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide a processor with an internal bus debugging function whereby bus accesses in the processor operating at a high speed can be traced with ease without increase in chip area.
A processor with an internal bus tracing function according to the present invention includes: an internal bus including at least an internal data bus transferring internal data and an address bus transmitting an address signal; a first internal memory, coupled with the internal bus, for storing the internal data on the internal data bus; a processing unit, coupled with the internal bus, for processing at least data on the internal data bus; and a second internal memory, coupled with the internal bus, for storing information on the internal bus in a trace mode and for storing data that the processing unit uses in an operating mode other than the trace mode.
The first and second internal memories are provided in the processor and in the trace mode, the second internal memory is used as a trace memory storing access information on the internal bus, while in an operating mode other than the trace mode, the first and second internal memories are used as internal memories forming an address space accessible by the processor, with the result that a utilization efficiency of memories is improved and a constituent element unnecessary in an actual operation can be prevented from existing in the processor, which makes increase in chip size of the processor restricted.
REFERENCES:
patent: 5560036 (1996-09-01), Yoshida
patent: 5826093 (1998-10-01), Assouad et al.
patent: 5978937 (1999-11-01), Miyamori et al.
patent: 6530076 (2003-03-01), Ryan et al.
patent: 6567932 (2003-05-01), Edwards et al.
patent: 6594782 (2003-07-01), Tagawa
patent: 2-208785 (1990-08-01), None
patent: 2-310738 (1990-12-01), None
Coleman Eric
McDermott & Will & Emery
Renesas Technology Corp.
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