Processor with sleep and deep sleep modes

Details Processor with sleep and deep sleep modes Processor with sleep and deep sleep modes

1997-05-07

2000-02-01

Sheikh, Ayaz R.

Electrical computers and digital processing systems: support

Computer power control

Power conservation

713300, G06F 132

Patent

active

060215003

ABSTRACT:
A processor has a clock generator circuit, a sleep pin that receives an external sleep signal, and a first interface circuit coupled to the clock generator circuit and the sleep pin. The clock generator circuit generates a core clock signal and a bus clock signal in response to an external clock signal. When the external sleep signal is asserted, the processor enters a sleep state when the core clock signal and the bus clock signal are in a first predetermined relationship with each other.

REFERENCES:
patent: 5473767 (1995-12-01), Kardach et al.
patent: 5511203 (1996-04-01), Wisor et al.
patent: 5560001 (1996-09-01), Kardach et al.
patent: 5630146 (1997-05-01), Conary et al.
patent: 5669003 (1997-09-01), Carmean et al.
patent: 5737615 (1998-04-01), Tetrick
patent: 5842029 (1998-11-01), Conary et al.
patent: 5862373 (1999-01-01), Pathikonda et al.

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