Processor provided with a slow-down facility through...

Computer graphics processing and selective visual display system – Computer graphics display memory system – Graphic display memory controller

Reexamination Certificate

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Details

C345S503000, C345S519000, C345S541000, C713S322000, C713S500000, C713S501000, C713S600000, C713S601000

Reexamination Certificate

active

06917365

ABSTRACT:
A processor executes image processing under control of a clock facility, such that a sequence of C effective clock cycles will effect a processing operation of a predetermined amount of image information. In particular, the processor has programming means for implementing programmable stall clock cycles interspersed between the effective clock cycles for implementing a programmable slowdown factor S, such that a modified number of C*S overall clock cycles will effect processing of the predetermined amount of digital signal information.

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patent: 5953685 (1999-09-01), Bogin et al.
patent: 6058450 (2000-05-01), LaBerge
patent: 6662278 (2003-12-01), Kahn et al.
“True-Motion Estimation with 3-D Recursive Search Block Matching”, by Gerard de Haan et al., IEEE Trans. CVST. Oct. 1993. pp. 368-379.

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