Computer graphics processing and selective visual display system – Computer graphics display memory system – Graphic display memory controller
Reexamination Certificate
2005-07-12
2005-07-12
Chauhan, Ulka J. (Department: 2676)
Computer graphics processing and selective visual display system
Computer graphics display memory system
Graphic display memory controller
C345S503000, C345S519000, C345S541000, C713S322000, C713S500000, C713S501000, C713S600000, C713S601000
Reexamination Certificate
active
06917365
ABSTRACT:
A processor executes image processing under control of a clock facility, such that a sequence of C effective clock cycles will effect a processing operation of a predetermined amount of image information. In particular, the processor has programming means for implementing programmable stall clock cycles interspersed between the effective clock cycles for implementing a programmable slowdown factor S, such that a modified number of C*S overall clock cycles will effect processing of the predetermined amount of digital signal information.
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Riemens Abraham Karel
Woods Nathan
Chauhan Ulka J.
Koninklijke Philips Electronics , N.V.
Ure Michael J.
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