Error detection/correction and fault detection/recovery – Data processing system error or fault handling – Reliability and availability
Patent
1997-02-19
1999-10-05
Le, Dieu-Minh T.
Error detection/correction and fault detection/recovery
Data processing system error or fault handling
Reliability and availability
714 30, 714718, 714733, G06F 1100
Patent
active
059616539
ABSTRACT:
An integrated chip having a DRAM embedded in logic is tested by an in-situ processor oriented BIST macro. The BIST is provided with two ROMS, one for storing test instructions and a second, which is scannable, that provides sequencing for the test instructions stored in the first ROM, as well as branching and looping capabilities. The BIST macro has, in addition, a redundancy allocation logic section for monitoring failures within the DRAM and for replacing failing word and/or data lines. By stacking the DRAM in 0.5 mb increments up to a 4.0 mb maximum or in 1.0 mb increments up to an 8 mb maximum, all of which are controlled and tested by the BIST macro, a customized chip design with a high level of granularity can be achieved and tailored to specific applications within a larger ASIC.
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Barth, Jr. John Edward
Dreibelbis Jeffrey Harris
Kalter Howard Leo
Kho Rex Ngo
Mori Yotaro
International Business Machines - Corporation
Le Dieu-Minh T.
Peterson Jr. Charles W.
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