Processor and method of testing a processor for hardware...

Details Processor and method of testing a processor for hardware... Processor and method of testing a processor for hardware...

2006-08-22

2006-08-22

Tsai, Henry W. H. (Department: 2183)

Electrical computers and digital processing systems: processing

Processing control

Specialized instruction processing in support of testing,...

C712S023000

Reexamination Certificate

active

07096347

ABSTRACT:
The instruction pipeline of a processor, which includes execution circuitry and instruction sequencing logic, receives a stream of instructions including a pipeline interlocking test instruction. The processor includes pipeline control logic that, responsive to receipt of the test instruction, interlocks the instruction pipeline as specified in the test instruction to prevent advancement of at least one first instruction in the instruction pipeline while permitting advancement of at least one second instruction in the instruction pipeline until occurrence of a release condition also specified by the test instruction. In response to the release condition, the pipeline control logic releases the interlock to enable advancement of said at least one instruction in the instruction pipeline. In this manner, selected instruction pipeline conditions, such a full queue or synchronization of instructions at certain pipeline stages, which are difficult to induce in a test environment through the execution of conventional instruction sets, can be tested.

REFERENCES:
patent: 5475852 (1995-12-01), Yoshida et al.
patent: 5708594 (1998-01-01), Iwashita et al.
patent: 6058470 (2000-05-01), Webb et al.
patent: 6732297 (2004-05-01), Oura

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