Electrical computers and digital processing systems: memory – Address formation – Address mapping
Reexamination Certificate
2005-06-01
2009-02-03
Ellis, Kevin L (Department: 2187)
Electrical computers and digital processing systems: memory
Address formation
Address mapping
C710S003000, C711S154000
Reexamination Certificate
active
07487327
ABSTRACT:
A processor employing device-specific memory address translation. In one embodiment, a processor may include a device interface configured to receive a memory access request from an input/output (I/O) device, where the request specifies a virtual memory address and a first requestor identifier (ID) that identifies the I/O device. The processor may also include an I/O memory management unit coupled to the device interface and configured to determine whether a virtual-to-physical memory address translation corresponding to the virtual memory address is stored within an I/O memory translation buffer. The I/O memory management unit may be further configured to determine whether a second requestor ID stored within the I/O memory translation buffer and corresponding to the memory address translation matches the first requestor ID. If the first and second requestor IDs do not match, the I/O memory management unit may disallow the memory access request and to signal an error condition.
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Microsoft Computer Dictionary, Microsoft Press, Redmond, WA, copyright 2002 by Microsoft Corporation.
Chang Bruce J.
Hetherington Ricky C.
Kahn David M.
McGee Brian J.
Saulsbury Ashley N.
Bradley Matthew
Ellis Kevin L
Kowert Robert C
Meyertons Hood Kivlin Kowert & Goetzel P.C.
Petro Anthony M.
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