Processor and interrupt handling method

Electrical computers and digital data processing systems: input/ – Interrupt processing – Processor status

Reexamination Certificate

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C718S102000

Reexamination Certificate

active

07877535

ABSTRACT:
Disclosed are a processor and an interrupt handling method. The processor of the present exemplary embodiments may include a plurality of processing elements and may predict whether a periodic interrupt occurs during a parallel processing mode before entering a mode in which the plurality of processing elements share a single task to process the single task in parallel. The processor may delay entering the parallel processing mode based on the prediction. The processor may reduce overhead that stores a context of the plurality of processing elements when the interrupt occurs.

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