Data processing: measuring – calibrating – or testing – Testing system
Reexamination Certificate
2002-12-18
2004-07-20
Barlow, John (Department: 2863)
Data processing: measuring, calibrating, or testing
Testing system
Reexamination Certificate
active
06766265
ABSTRACT:
BACKGROUND
1. Technical Field
The present invention relates generally to semiconductor technology and more specifically to semiconductor research and development and processing clustered data.
2. Background Art
Currently, electronic products arc used in almost every aspect of life, and the heart of these electronic products is the integrated circuit. Integrated circuits are used in everything from airplanes, televisions and wristwatches to cameras and microwaves.
Integrated circuits are made in and on silicon wafers by extremely complex systems that require the coordination of hundreds or even thousands of precisely controlled processes to produce a finished semiconductor wafer. Each finished semiconductor wafer has hundreds to tens of thousands of integrated circuits, each worth hundreds or thousands of dollars.
The ideal would be to have every one of the integrated circuits on a wafer functional and within specifications, but because of the sheer numbers of processes and minute variations in the processes, this rarely occurs. “Yield” is the measure of how many “good” integrated circuits there are on a wafer divided by the total number of integrated circuits formed on the wafer divided by the maximum number of possible good integrated circuits on the wafer. A 100% yield is extremely difficult to obtain because minor variations, due to such factors as timing, temperature, and materials, substantially affect a process. Further, one process often affects a number of other processes, often in unpredictable ways.
In a manufacturing environment, the primary purpose of experimentation is to increase the yield. Experiments are performed in-line and at the end of the production line with both production wafers and experimental wafers. However, yield enhancement methodologies in the manufacturing environment produce an abundance of very detailed data for a large number of wafers on processes subject only to minor variations. Major variations in the processes are not possible because of the time and cost of using production equipment and production wafers. Setup times for equipment and processing time can range from weeks to months, and processed wafers can each contain hundreds of thousands of dollars worth of integrated circuits.
The learning cycle for the improvement of systems and processes requires coming up with an idea, formulating a test(s) of the idea, testing the idea to obtain data, studying the data to determine the correctness of the idea, and developing new ideas based on the correctness of the first idea. The faster the correctness of ideas can be determined, the faster new ideas can be developed. Unfortunately, the manufacturing environment provides a slow learning cycle because of manufacturing time and cost.
Recently, the great increase in the complexity of integrated circuit manufacturing processes and the decrease in time between new product conception and market introduction have both created the need for speeding up the learning cycle.
This has been accomplished in part by the unique development of the integrated circuit research and development environment. In this environment, the learning cycle has been greatly speeded up and innovative techniques have been developed that have been extrapolated to high volume manufacturing facilities.
To speed up the learning cycle, processes are speeded up and major variations are made to many processes, but on only a few wafers arc processed to reduce cost. The research and development environment has resulted in the generation of tremendous amounts of data and analysis for all the different processes and variations. This, in turn, has required a large number of engineers to do the analysis. With more data, the answer always has been to hire more engineers.
However, this has not been the way to answer to some major of the problems.
The problems include, but are not limited to, the difficulty in analyzing data and charts where the axes of the charts are in one or two ranges and the data is clustered into a number of distinct data clusters.
The problems include, but are not limited to, the presence of data values significantly outside of the main distributions, which cause distortions of the scale of the charts.
The problems include, but are not limited to, the difficulty of joining a plurality of data tables whose row descriptors do not have unique matches.
Solutions to these problems have been long sought but prior developments have not taught or suggested any solutions and, thus, solutions to these problems have long eluded those skilled in the art.
DISCLOSURE OF THE INVENTION
The present invention provides a method for processing tester information. The number of clusters of data in the tester information is determined to determine the number of data clusters. A basis is determined from the tester information to be used for plotting the data clusters. The data clusters are plotted on a plurality of trellis charts to form a trellising plot with a trellis of trellis charts. This system provides the ability to quickly and efficiently analyze tester information data through the trellising of clustered data and thus increase output and tested device integrity in production.
Certain embodiments of the invention have other advantages in addition to or in place to of those mentioned above. The advantages will become apparent to those skilled in the art from a reading of the following detailed description when taken with reference to the accompanying drawings.
REFERENCES:
patent: 5793940 (1998-08-01), Tajima et al.
patent: 2002/0121915 (2002-09-01), Montull et al.
patent: 2003/0101009 (2003-05-01), Seem
patent: 2003/0192003 (2003-10-01), Das et al.
Miller et al., Deterministic Annealing for Trellis Quantizer and HMM design Using Baum-Welch Re-estimation, 1994, IEEE, vol. 5, p. V/261-4.*
Haystack Syndrome Avoidance on Massive Correlation for Probe vs. E-test data through the Concurrent Use of Tree Base Models and Trellis Graphics, 1999,IEEE, pp. 76-79.
Erhardt Jeffrey P.
Shetty Shivananda S.
Advanced Micro Devices , Inc.
Barlow John
Ishimaru Mikio
Pretlow Demetrius
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