Processing techniques for making a dual floating gate EEPROM cel

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate

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438261, 438262, 438263, 438264, 438265, 257202, H01L 21336

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active

061035734

ABSTRACT:
An EEPROM system having an array of memory cells that individually include two floating gates, bit line source and drain diffusions extending along columns, steering gates also extending along columns and select gates forming word lines along rows of floating gates. The dual gate cell increases the density of data that can be stored. Rather than providing a separate steering gate for each column of floating gates, an individual steering gate is shared by two adjacent columns of floating gates that have a diffusion between them. Processing methods of forming such a cell array include two etching steps to separate strips of conductive material into individual floating gates that are self-aligned with source/drain diffusions and other gate elements. In one embodiment, this is accomplished by two etching steps with separate masks. In another embodiment, a reference dielectric mask is first formed over the conductive material layer strips and used as a reference for two etching masks that are aligned with each other. In a further embodiment, isolation of the memory cells is provided in the column direction by forming rectangular trenches in the substrate between cells that are filled with dielectric. Specific processing techniques also have applications to form single floating gate EEPROM cell arrays, other types of memory cells and integrated circuit elements.

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