Processing of self-modifying code in multi-address-space and...

Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories

Reexamination Certificate

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C711SE12078

Reexamination Certificate

active

07822924

ABSTRACT:
A method and system of storing to an instruction stream with a multiprocessor or multiple-address-space system is disclosed. A central processing unit may cache instructions in a cache from a page of primary code stored in a memory storage unit. The central processing unit may execute cached instructions from the cache until a serialization operation is executed. The central processing unit may check in a message queue for a notification message indicating potential storing to the page. If the notification message is present in the message queue, cached instructions from the page are invalidated.

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Notification of Transmittal of the International Search Report and the Written Opinion of the International Searching Authority, or the Declaration; PCT/US2005/037787.
“Reduction of Cache Coherence Traffic in MP Systems Via Large Block Authority”, IBM Technical Disclosure Bulletin, Armonk, NY, US, vol. 33, No. 2, Jul. 1990; pp. 398-406.

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