Semiconductor device manufacturing: process – Chemical etching – Combined with coating step
Patent
1997-08-14
1999-11-02
Everhart, Caridad
Semiconductor device manufacturing: process
Chemical etching
Combined with coating step
438713, 438714, 438673, H01L 21465
Patent
active
059769858
ABSTRACT:
Methods of forming contact openings over a node location and related integrated circuitry are described. In one aspect of the invention, a node location is formed within a semiconductive substrate adjacent an isolation oxide region. A layer of material is formed over the node location and a contact opening is etched through the layer of material to outwardly expose a node location planar upper surface. In one preferred implementation, the contact opening includes an inner surface portion which faces generally transversely away from the isolation oxide region and which defines an angle with the node location upper surface which is greater at a bottom of the contact opening than at a top of the contact opening. In another preferred implementation, the contact opening includes sidewall portions which define a profile which having a non-uniform degree of taper between the contact opening top and bottom. In another preferred implementation, the tapering of the contact opening is effectuated by modifying at least one etching parameter at an intermediate etching point and continuing the etching to outwardly expose the node location.
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A. Shinohara et al., "A New Self-Aligned Contact Technology for LDD MOS Transistors", Extended Abstracts of the 17th Conference on Solid State Devices and Materials, Tokyo, Japan, 1985, pp. 12-15.
Donohoe Kevin G.
Prall Kirk D.
Everhart Caridad
Micro)n Technology, Inc.
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