Processes providing high and low threshold p-type and n-type...

Details Processes providing high and low threshold p-type and n-type... Processes providing high and low threshold p-type and n-type...

2006-10-03

2009-08-04

Nhu, David (Department: 2895)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S197000, C438S289000, C257SE21050, C257SE21315, C257SE21633

Reexamination Certificate

active

07569449

ABSTRACT:
Methods of fabricating negative-channel metal-oxide semiconductor (NMOS) devices and positive-channel metal-oxide semiconductor (PMOS) devices having complementary threshold voltages are described. Elements of lower-threshold voltage NMOS devices are formed at first locations on a substrate. Elements of higher-threshold voltage PMOS devices are formed at second locations on the substrate. Elements of higher-threshold voltage NMOS devices and elements of lower-threshold PMOS devices are formed by adding a same amount of p-type dopant at selected locations chosen from the first and second locations.

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USPTO Notice of Allowance for U.S. Appl. No. 10/306,414, dated May 12, 2006.
USPTO Final Rejection for U.S. Appl. No. 10/306,414, dated Feb. 8, 2006.
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