Processes for making a barrier between a dielectric and a...

Details Processes for making a barrier between a dielectric and a... Processes for making a barrier between a dielectric and a...

2001-07-23

2004-01-13

Zarabian, Amir (Department: 2822)

Semiconductor device manufacturing: process

Coating of substrate containing semiconductor region or of...

Insulative material deposited upon semiconductive substrate

C438S240000, C438S769000, C438S770000, C438S775000, C438S786000

Reexamination Certificate

active

06677254

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates generally to methods for improving the interface between a dielectric and a conductor in semiconductor devices.
BACKGROUND OF THE INVENTION
The reliable operation of integrated circuits is critically dependent on the reliability of the increasingly thin dielectric layers used in circuit devices. As transistors have become smaller and more densely packed, the dielectrics have become thinner. Capacitor and gate dielectrics are often less than 80 angstroms in thickness, sometimes approaching 50 angstroms or less. For integrated circuits to work, these thin layers in each of thousands of different transistors must provide sufficient capacitance to drive the device, protect the channel from migration of impurities and avoid production of charge traps at their interfaces. These demanding requirements may soon exceed the capacities of conventional silicon oxide layers. Silicon oxide layers less than 2 nm may have prohibitively large leakage currents.
Efforts to replace silicon oxide as the gate dielectric have thus far proved less than satisfactory. Because of its relatively low dielectric constant (approx. 3.9), the largest capacitance obtainable with a thin layer of silicon oxide is about 25 fF/&mgr;m
2
. This limits the scaling of transistors to smaller sizes because the capacitance will not be sufficient to drive the device. Higher dielectric constant tantalum oxide has been tried, but results are poor due to a high density of charge traps at the dielectric/silicon interface. Composite layers of SiO
2
/Ta
2
O
5
and SiO
2
/Ta
2
O
5
/SiO
2
were tried, but the necessary resulting thicknesses limit the capacitance which can be obtained. Efforts have also been made to prevent charge traps by depositing a thin layer of silicon nitride between the silicon and the tantalum oxide. But the nitride layer also reduces the capacitance and thus limits scaling of the device. See U.S. Pat. No. 5,468,687 issued to D. Carl et al on Nov. 21, 1995 and Y. Momiyama et al, “
Ultra
-
Thin Ta
2
O
5
/SiO
2
Gate Insulator with TiN Gate”,
1997
Symposium on VLSI Technology,
Digest of Technical Papers, pp. 135-136. Furthermore, efforts to make capacitors using Ta
2
O
5
films deposited by reactive sputtering, chemical vapor deposition (CVD), and plasma enhanced chemical vapor deposition have produced devices having high leakage currents and low breakdown voltages. See T Aoyama et al., “
Leakage current mechanism of amorphous and polycrystalline Ta
2
O
5
films grown by chemical vapor deposition”, J. Electrochem. Soc.,
Vol. 143, No. 3, pp. 977-983 (March 1996).
Furthermore, these Ta
2
O
5
films degraded upon thermal annealing above 200° C. with irreversible increases in the temperature coefficient of capacitance (TCC) and the dissipation factor. See J. M. Schoen et al, “The correlation between temperature coefficient of capacitance and dielectric loss in tantalum and tantalum-aluminum anodic oxides,” J. Electrochem. Soc., Vol. 119, pp. 1215-1217 (September 1972). This degradation is believed to be due to the diffusion of electrode metal atoms into the dielectric and diffusion of oxygen out, creating oxygen deficiency defects.
A variety of electrode metals have been tried to overcome degradation problems, but with less than satisfactory results. Chromium was tried but specifically rejected. See M. Peters et al., “
Thermally stable thin film tantalum pentoxide capacitor”, Proc. of the International Conference on Multichip Modules,
Denver, pp. 94-99 (April 1996).
Ruthenium (Ru) has been employed for both the bottom and top electrodes in a capacitive structure, with mixed results. Referring to
FIG. 1
, a film of Ta
2
O
5
104
was deposited over the bottom electrode
102
as the dielectric layer
104
in this stack
100
. After annealing of the dielectric layer
104
in an oxygen rich environment, a top electrode
106
was deposited over the dielectric layer
104
. The interface between the top electrode
106
and the dielectric
104
can be problematic, as reaction between the dielectric layer and the ruthenium may occur, leading to mixing of phases between the two layers and oxygen scavenging from the dielectric layer which reduces the overall dielectric constant.
Similarly, tungsten (W) and other metals run the same risk of phase mixing with the dielectric layer and oxidation scavenging of the dielectric layer upon deposition over the dielectric layer. When nitrides of metals, such as TiN or TaN are used, and NH
3
is used in forming the nitride as it is being deposited, the NH
3
in the process can act to reduce the dielectric layer, which also degrades its performance.
As such, there is a need for improved processes for employing high k dielectrics in thin films to make semiconductor devices that will not degrade due to the diffusion of electrode metal atoms into the dielectric and diffusion of oxygen out, creating oxygen deficiency defects. There is also a need to produce these devices at temperatures which will not degrade the dielectric or metals in the devices.
SUMMARY OF THE INVENTION
In view of the foregoing background, the present invention is directed to improved processes for making interfaces between high k dielectrics and conducting layers that will provide superior performance to those known in the art, and products resulting therefrom.
The present invention includes a method of making a barrier on a high k dielectric material by providing a substrate having an upper surface comprising a high k dielectric material; remotely generating a plasma using a nitrogen containing source; and flowing the plasma over the upper surface comprising a high k dielectric material to form an oxynitride layer on the upper surface.
At least the upper surface of the substrate may be annealed in an oxygen rich environment prior to flowing the plasma.
In an example where the high k dielectric material comprises Ta
2
O
5
, the nitrogen containing source may comprise N
2
and the oxynitride layer which is formed comprises TaON.
In another example, a remote plasma is generated using NH
3
as a nitrogen containing source, and a TaON layer is formed by flowing the plasma over the high k material.
In either of the above examples, a remote plasma may be generated using an oxygen containing source, and the plasma is flowed over the oxynitride layer to saturate any reduced species remaining in the oxynitride layer.
A conducting layer is then deposited over the oxynitride layer, by chemical vapor deposition, for example. In the case of a capacitor stack arrangement, the conducting layer is a top electrode. The conducting layer may comprise TiN, for example.
Generally, the processes according to the present invention are conducted within a temperature range of about 300° to 700° C. and are thus appropriate for low thermal budget applications.
In another example, a layer of TiN is deposited over a high k dielectric material, by chemical vapor deposition, for example. A remote plasma is formed using an oxygen containing source, and the plasma is flowed over the TiN layer to form an oxynitride layer on the upper surface.
At least the upper surface of the high k dielectric material may be annealed prior to depositing the layer of TiN.
The oxygen containing source may be oxygen or N
2
O, for example.
The high k dielectric material may comprise Ta
2
O
5
, for example, in which case the oxynitride layer comprises TaON.
A conducting layer is next deposited over the oxynitride layer. In the case of a capacitor stack arrangement, the conducting layer is a top electrode. The conducting layer may comprise TiN, for example.
A stack capacitor device comprising a high k dielectric layer, a barrier layer overlying the high k dielectric layer and having been formed, at least in part by a remote plasma process; and a top electrode overlying the barrier layer is disclosed.
The high k dielectric layer may comprise Ta
2
O
5
. The barrier layer may comprise TaON or TiON, for example. The top electrode may comprise TiN.
The present invention provides methods for improving the performance of

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