Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2001-08-10
2004-11-16
Nelms, David (Department: 2818)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S258000, C438S259000, C438S260000
Reexamination Certificate
active
06818504
ABSTRACT:
BACKGROUND OF THE INVENTION
A layout view of a previously known floating-gate non-volatile memory cell transistor
10
in a memory array is shown in FIG.
1
A. Cell transistor
10
is formed by the intersection of active area
13
and gate
12
. Contact
11
is a contact to the drain or the source of cell
10
(e.g., in NOR architecture, contact
11
is usually the contact to the drain). Contact
11
is spaced a minimum-required distance away from gate
12
as shown in FIG.
1
A. This minimum-required distance can be for instance 1000-1400 angstroms for 0.25 &mgr;m technology, and is dictated by the contact mis-alignment tolerance of a process technology.
Further details of prior art cell transistor
10
are shown in FIG.
2
.
FIG. 2
is a cross-section view of cell
10
along a vertical axis through contact
11
with respect to
FIG. 1A
, and a cross-section view of a periphery MOS transistor
20
. An example of cell transistor
10
includes a stacked gate
13
including a tunnel oxide layer, a first polysilicon layer that comprises a floating gate, an oxide
itride/oxide (ONO) composite layer, a second polysilicon layer
12
and a tungsten silicide (WSi
x
) layer that comprise a control gate, and dielectric layers PE-TEOS, PE-Nitride, and ARC Oxynitride. Periphery transistor
20
includes gate layers
16
having a gate oxide, a second layer polisilicon, a tungsten silicide layer, and dielectrics layers PT-TEOS, PE-Nitride, and ARC Oxynitride. Stacked gate
13
may be formed using a gate mask and gate etch, followed by cell self-aligned mask and self-aligned etch (SAE). Next, drain and source regions including drain region
14
are formed for each of memory cell
10
array and peripheral transistor
20
.
Oxide spacers including spacers
15
A and
15
B having a thickness in the range of 500-1400 A are formed adjacent to each gate stack
13
typically by depositing a high temperature oxide (HTO) layer and etching back. Spacer
15
A is part of the spacing between each edge of gate stack
13
and the contact to drain
14
. Gate to contact spacing is typically bigger than the spacer width, so that during the steps of contact mask and etch, the spacer width is preserved even considering contact mask misalignment.
A separate contact mask is used to form the contact to drain
14
. After the contact mask is applied, etching is performed to form contact holes over the drain and source regions. In a typical NOR architecture, a contact to every source is provided, for instance in the case of source local interconnect using, for example, tungsten local interconnect (WLI). Otherwise, a contact to the source line can be provided using source pick-up for the row of every 8 or 16 cells. Due to contact mask misalignment, some of the drain contact holes may become offset from their desired location to the left or to the right in
FIG. 2
, causing portions of spacer
15
A or
15
B to be etched away. If all of spacer
15
A or
15
B is etched, the subsequently formed contact will make electrical contact with the adjacent gate(s), which prevents the transistor from operating in the desired manner. Thus, the gate-to-contact spacing should be wide enough to account for potential misalignment between gate and contact masks. The wide contact-to-gate spacing results in a larger cell size.
Spacer
15
C is also formed adjacent to peripheral transistor
16
, as shown in
FIG. 2
, at the same time spacers
15
A and
15
B are formed. Highly doped N+ or P+ source/drain regions such as region
17
are formed in previously formed LDD or DDD regions after the formation of spacer
15
C. The width of spacer
15
C determines the lateral spacing between the outer edge of the N+/P+ regions and an outer edge of the LDD or DDD regions. This spacing is labeled as “x” in FIG.
2
. Spacer
15
C must be wide enough (e.g., ~1000-1400 angstroms for 0.25 &mgr;m technology, 3V power supply) to provide for the necessary lateral distance “x” between the outer edge of the low doped drain (LDD) region and its inner N+/P+ region in low voltage transistors (or the outer edge of the double doped drain (DDD) region and its inner N+/P+ region in high voltage transistors) to assure a high breakdown voltage and robust hot carrier injection reliability performance.
Depending on different factors such as the process technology, the application for the memory, and the required operating supply voltages, the spacing “x” needs to be varied. For example, where the memory is to be used in a portable device operating on a 2 v supply voltage, the spacing “x” can be made smaller for the low voltage transistors, while in the case of a 3 v operating supply voltage, the spacing needs to be increased. If smaller spacing “x” is used for higher supply voltages, e.g. same “x” for 3V as for 2V operation, the transistor may require longer channel length to improve HEI (hot electron injection ) reliability. That in turn will decrease transistor drive current and overall performance. Accommodating such variations in a single process technology results in a complex process technology with multiple types of periphery transistors with different layout design rules (LDR). Such complex process technology increases manufacturing cost while complicating the circuit design process, because similar transistor blocks (circuits) with different LDR will have to be laid out separately for products with different power supply voltages.
It would therefore be desirable to reduce the width of the spacers along the side walls of the cell gate stack to reduce the cell size, while a mechanism is provided to allow varying the spacing “x” without unduly complicating the process steps, all in a self-aligned-contact non-volatile memory cell technology. This is also desirable for embedded applications, because accommodating various requirements for various transistors can be made easier.
BRIEF SUMMARY OF THE INVENTION
The present invention provides structures and methods for flash memory transistors that are formed with self-aligned drain/source contacts. The flash transistors are formed with a plurality of gate layers. An etch resistant layer is deposited on top of the gate layers in the memory array transistors and on the gate layers of peripheral transistors. An additional oxide spacer may be formed on the etch resistant layer to control the implantation of highly doped N+/P+ source and drain diffusion regions. Contact etching is then performed to form contact holes to the drain and source regions of the memory and peripheral transistors. The etch resistant layer prevents the contact etchants from completely etching away the protective etch resistant layer surrounding the gate layers of the transistors. Therefore, the drain/source contacts when formed do not make electrical contact with the gate layers of the transistors, because enough of the etch resistant layer remains after etching to provide sufficient insulation. Thus, the drain and source contacts are self-aligned with the gates of the transistors.
The structures and methods for flash cell transistors and peripheral transistors of the present invention are advantageous, because the spacing between the drain/source contacts and the gate layers can be greatly reduced due to the self-aligned nature of the contact etching process. Therefore, spacing between the flash memory transistors can be reduced, providing a substantial increase in the density of the transistors in the memory array. Also, the thickness of the oxide layer deposited on top of the etch resistant layer can be chosen to optimize the channel length and the position of the N+/P+ drain/source diffusion regions in the peripheral transistors to maintain a high breakdown voltage and robust hot carrier injection reliability performance.
REFERENCES:
patent: 5641696 (1997-06-01), Takeuchi
patent: 6051465 (2000-04-01), Kato et al.
patent: 6071775 (2000-06-01), Choi et al.
Chou Kai-Cheng
Rabkin Peter
Wang Hsingya Arthur
Berry Renee R.
Cahill Steven J.
Hynix Semiconductor America, Inc.
Townsend and Townsend / and Crew LLP
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