Electronic digital logic circuitry – Clocking or synchronizing of logic stages or gates
Reexamination Certificate
2008-10-30
2010-02-23
Cho, James (Department: 2819)
Electronic digital logic circuitry
Clocking or synchronizing of logic stages or gates
C326S033000
Reexamination Certificate
active
07667497
ABSTRACT:
A circuit having dynamically controllable power. The circuit comprises a plurality of pipelined stages, each of the pipelined stages comprising two clocking domains, a plurality of switching circuits, each switching circuit being connected to one of the pipelined stages, first and second power sources connected to each of the plurality of pipelined stages through the switching circuits, the first power source supplying a first voltage and the second power source supplying a second voltage, wherein the first and second power sources each may be applied to a pipelined stage independently of other pipelined stages, first and second complementary clocks, and a plurality of latches connected to the first and second complementary clocks and to the plurality of pipelined stages for proving latch-based clocking to control the first and second clocking domains and to enable time-borrowing across the plurality of switching circuits. The first voltage differs from the second voltage and the plurality of pipelined stages interpolates between the first and second voltages to provide differing effective voltages between the first and second voltages.
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Brooks David
Liang Xiaoyao
Wei Gu-Yeon
24IP Law Group
Cho James
DeWitt Timothy R.
President and Fellows of Harvard College
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