Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Patent
1997-04-01
1998-12-29
Monin, Donald
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
257360, 257537, H01L 2976, H01L 2362
Patent
active
058545042
ABSTRACT:
An improved ESD cell provides in the worst case 2,000 volts HBM ESD protection using an NMOS transistor in a lightly-doped drain process. An NMOS transistor has its source connected to ground, and its drain connected through a polysilicon resistor to a pad of an integrated circuit. The pad is also connected by metal to an n+ pocket tap of an n-type epitaxial layer formed on a p-type substrate. The connection of pad metal to the pocket tap forms a second parasitic lateral bipolar junction transistor (BJT) having as a base the p-type well, having an emitter the source of the NMOS transistor, and having as its collector the pocket tap. The parasitic transistor turns on at the right moment and is able to shunt more current around the polysilicon resistor, thus giving a dramatic increase in ESD protection. In a worst case, the ESD cell can pass at a minimum of 2,000 volts, and the expected range of HBM ESD values is between 2,500 volts and 3,000 volts depending upon process variations. Use of a polysilicon resistor allows the device to be driven into avalanche without destroying itself, and enables the parasitic transistor to be turned on. The ESD cell is tolerant of varying processes.
REFERENCES:
patent: 4821096 (1989-04-01), Maloney
patent: 5392186 (1995-02-01), Alexander et al.
patent: 5438213 (1995-08-01), Tailliet
patent: 5504362 (1996-04-01), Pelella et al.
patent: 5508548 (1996-04-01), Tailliet
patent: 5534723 (1996-07-01), Iwai et al.
patent: 5561312 (1996-10-01), Nozoe et al.
Duvvury, et al., ESD Design Considerations for ULSI, 1985, presented at the EOS/ESD Symposium.
Hu, et al., Hot-Electron-Induced MOSFET Degradation Model, Monitor, and Improvement, Feb. 1985, IEEE Transactions on Electron Devices, vol. ED 32. No. 2.
Gadi Krieger, Thermal Response of Integrated Circuit Input Devices to an Electrostatic Energy Pulse, Apr. 1987, IEEE Transactions on Electron Devices, vol. ED-34, No. 4.
Maxim Integrated Products Inc.
Monin Donald
LandOfFree
Process tolerant NMOS transistor for electrostatic discharge pro does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Process tolerant NMOS transistor for electrostatic discharge pro, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Process tolerant NMOS transistor for electrostatic discharge pro will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-1426704