Process to minimize polysilicon gate depletion and dopant...

Details Process to minimize polysilicon gate depletion and dopant... Process to minimize polysilicon gate depletion and dopant...

2005-05-24

2005-05-24

Zarneke, David (Department: 2829)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C257S288000

Reexamination Certificate

active

06897102

ABSTRACT:
A method of preparing a polysilicon gate to minimize gate depletion and dopant penetration and to increase conductivity is revealed. Several monolayers of atomic are condensed onto a gate dielectric. Polysilicon is deposited onto the calcium and patterned in a standard way. The exposed calcium is then removed by raising the temperature to approximately 600° C. The calcium remaining between the gate dielectric and the polysilicon blocks channeling of dopant to minimize depletion and penetration, increase conductivity, and allow for longer and higher-temperature annealing.

REFERENCES:
patent: 6132492 (2000-10-01), Hultquist et al.

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