Process to manufacture high density ULSI ROM array

Details Process to manufacture high density ULSI ROM array Process to manufacture high density ULSI ROM array

1998-09-18

1999-12-07

Trinh, Michael

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

438271, 438276, 438278, 438589, H01L 21336, H01L 218236

Patent

active

059982675

ABSTRACT:
A compact MOS array including word lines perpendicular to and overlapping bit lines, is fabricated by etching trenches in the underlying silicon and then forming successive bit lines within the trenches and upon the intervening mesas. Subsequent implantation of dopant into trench sidewalls creates channel regions oriented at an angle relative to the horizontal bit lines. Disposing successive diffused bit lines in vertically separated planes enables fabrication of ROM cells having full channel lengths which occupy a smaller surface area. Tilted ion implantation may be utilized to introduce dopant into channel regions.

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patent: 5904526 (1999-05-01), Wen et al.
Bergemont, et al., High Density ROM Cell Structure for ULSI ROM Array, Co-pending U.S. Application 09/156,941 filed Sep. 18, 1998.

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