Process to improve temperature uniformity during RTA by depositi

Details Process to improve temperature uniformity during RTA by depositi Process to improve temperature uniformity during RTA by depositi

1998-09-04

2000-08-08

Booth, Richard

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

438592, 438928, H01L 21336, H01L 213205, H01L 214763

Patent

active

061001503

ABSTRACT:
Methods are disclosed for depositing an in situ polysilicon layer on the back of a semiconductor wafer to reduce the temperature at the edge of the wafer during rapid thermal annealing (RTA). The reduced temperature results in decreased boron penetration at the edge of the wafer and a more uniform silicide resistance and threshold voltage across the wafer.

REFERENCES:
patent: 4608096 (1986-08-01), Hill
patent: 4621413 (1986-11-01), Lowe et al.
patent: 4853345 (1989-08-01), Himelick
patent: 5395770 (1995-03-01), Miki et al.
patent: 5496742 (1996-03-01), Yamada
patent: 5605602 (1997-02-01), DeBusk
patent: 5656510 (1997-08-01), Chrapacz et al.
patent: 5698891 (1997-12-01), Tomita et al.
patent: 5716873 (1998-02-01), Prall et al.
patent: 5716875 (1998-02-01), Jones, Jr. et al.
patent: 5739067 (1998-04-01), DeBusk et al.
patent: 5894037 (1999-04-01), Kikuchi et al.

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