Process to improve read disturb for NAND flash memory devices

Details Process to improve read disturb for NAND flash memory devices Process to improve read disturb for NAND flash memory devices

1999-09-20

2002-04-30

Fourson, George (Department: 2823)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S264000, C438S594000, C438S770000

Reexamination Certificate

active

06380033

ABSTRACT:

TECHNICAL FIELD
The present invention generally relates to improved methods of making flash memory devices such as EEPROMs. More particularly, the present invention relates to methods of making NAND type flash memory devices characterized by improved read disturb properties.
BACKGROUND ART
Semiconductor devices typically include multiple individual components formed on or within a substrate. Such devices often comprise a high density section and a low density section. For example, as illustrated in prior art
FIG. 1
a
, a memory device such as a flash memory
10
comprises one or more high density core regions
11
and a low density peripheral portion
12
on a single substrate
13
. The high density core regions
11
typically consist of at least one M×N array of individually addressable, substantially identical floating-gate type memory cells and the low density peripheral portion
12
typically includes input/output (I/O) circuitry and circuitry for selectively addressing the individual cells (such as decoders for connecting the source, gate and drain of selected cells to predetermined voltages or impedances to effect designated operations of the cell such as programming, reading or erasing).
The memory cells within the core portion
11
are coupled together in a NAND-type circuit configuration, such as, for example, the configuration illustrated in prior art
FIG. 1
b
. Each memory cell
14
has a drain
14
a
, a source
14
b
and a stacked gate
14
c
. A plurality of memory cells
14
connected together in series with a drain select transistor at one end and a source select transistor at the other end to form a NAND string as illustrated in prior art
FIG. 1
b
. Each stacked gate
14
c
is coupled to a word line (WL
0
, WL
1
, . . . , WLn) while each drain of the drain select transistors are coupled to a bit line (BL
0
, BL
1
, . . . , BLn). Lastly, each source of the source select transistors are coupled to a common source line Vss. Using peripheral decoder and control circuitry, each memory cell
14
can be addressed for programming, reading or erasing functions.
Prior art
FIG. 1
c
represents a fragmentary cross section diagram of a typical memory cell
14
in the core region
11
of prior art
FIGS. 1
a
and
1
b
. Such a cell
14
typically includes the source
14
b
, the drain
14
a
and a channel
15
in a substrate or P-well
16
; and the stacked gate structure
14
c
overlying the channel
15
. The stacked gate
14
c
further includes a thin gate dielectric layer
17
a
(commonly referred to as the tunnel oxide) formed on the surface of the P-well
16
. The stacked gate
14
c
also includes a polysilicon floating gate
17
b
which overlies the tunnel oxide
17
a
and an interpoly dielectric layer
17
c
overlies the floating gate
17
b
. The interpoly dielectric layer
17
c
is often a multilayer insulator such as an oxidenitride-oxide (ONO) layer having two oxide layers sandwiching a nitride layer. Lastly, a polysilicon control gate
17
d
overlies the interpoly dielectric layer
17
c
. The control gates
17
d
of the respective cells
14
that are formed in a lateral row share a common word line (WL) associated with the row of cells (see, for example, prior art
FIG. 1
b
). In addition, as highlighted above, the drain regions
14
a
of the respective cells in a vertical column are connected together by a conductive bit line (BL). The channel
15
of the cell
14
conducts current between the source
14
b
and the drain
14
a
in accordance with an electric field developed in the channel
15
by the stacked gate structure
14
c.
The process for making such NAND type flash memory devices includes numerous individual processing steps, as there are numerous elements of the flash memory devices. There are numerous concerns associated with making flash memory devices that provide consistent performance and reliability. There are also numerous concerns associated with making high quality elements that constitute flash memory devices. For example, tunnel oxides are important elements since electrons tunnel therethrough during erase operations. On one hand, a relatively thick tunnel oxide results in slow erase performance. A relatively thick tunnel oxide is therefore undesirable. On the other hand, the continued trend of scaling (towards miniaturization) often undermines the ability of a tunnel oxide to handle increased amounts of electrical stress.
In particular, during electrical programming and erasing, a large amount of hot electrons are generated. Programming and erasing is often referred to as cycling. Cycling results in undesirably high levels of electron trapping in the tunnel oxide. Typically, as the number of cycles imposed on a flash memory cell increases, the number of carriers trapped in the tunnel oxide increases. Increased numbers of carriers trapped in the tunnel oxide, in turn, leads to increased erase/program times (to ensure an entire array of cells is completely charged or discharged) and/or shifts in transconductance causing charge loss. In the programmed state, defects in the tunnel oxide causes charge loss which in turn causes read disturb problems decreasing the reliability of flash memory cells. It is difficult to provide a flash memory cell capable of conducting more than about 10
5
program/erase cycles without showing significant read disturb problems.
In view of the aforementioned concerns and problems, there is a need for flash memory cells of improved quality and more efficient methods of making such memory cells. In particular, flash memory cells capable of handling hot-electron stress during extended cycling are desired.
SUMMARY OF THE INVENTION
As a result of the present invention, non-volatile flash memory device fabrication is improved thereby producing devices having improved reliability. By employing the methods of the present invention which provide for specific parameters for making tunnel oxides and select gate transistor oxides, the formation of a flash memory devices characterized by reduced read disturb problems is facilitated. More specifically, the methods of the present invention minimize and/or eliminate read disturb problems in NAND type flash memory devices by minimizing and/or eliminating electron trapping in the tunnel oxide. The methods of the present invention further enable the formation of flash memory devices capable of more than about 10
5
program/erase cycles without significant read disturb problems.
In one embodiment, the present invention relates to a method of forming a NAND type flash memory device capable of more than about 1×10
5
program/erase cycles without significant read disturb problems involving the steps of growing a first oxide layer over at least a portion of a substrate, the substrate including a flash memory cell area and a select gate area; removing a portion of the first oxide layer in the flash memory cell area of the substrate; growing a second oxide layer over at least a portion of the substrate in the flash memory cell area and over at least a portion of the a first oxide layer in the select gate area; annealing the first oxide layer and the second oxide layer under an inert gas and at least one of N
2
O and NO for a period of time from about 1 minute to about 15 minutes; depositing a first in situ doped amorphous silicon layer over at least a portion of the second oxide layer; depositing a dielectric layer over at least a portion of the first in situ doped amorphous silicon layer; depositing a second doped amorphous silicon layer over at least a portion of the dielectric layer; and forming a flash memory cell in the flash memory cell area of the substrate and a select gate transistor in the select gate area substrate, the flash memory cell comprising the second oxide layer, the first in situ doped amorphous silicon layer, the dielectric layer, and the second doped amorphous silicon layer, and the select gate transistor comprising the first oxide layer, the second oxide layer, the first in situ doped amorphous silicon layer, the dielectric layer, and the second doped amor

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