Process to form CMOS devices with higher ESD and hot carrier imm

Details Process to form CMOS devices with higher ESD and hot carrier imm Process to form CMOS devices with higher ESD and hot carrier imm

1998-01-26

2000-05-30

Nelms, David

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

438199, 438659, 438766, H01L 21336

Patent

active

060690313

ABSTRACT:
The process includes the following steps. At first, an isolation region in the semiconductor substrate is formed to separate the semiconductor substrate into a PMOS region, a NMOS region, and an ESD protective region. Gate structures are then formed on the PMOS region, the NMOS region, and the ESD protective region. A doping process is performed to the NMOS region and the ESD protective region, with first dopants for a lightly doped region in the semiconductor substrate. Another doping process is performed to the PMOS region and the ESD protective region, with second dopants for a PMOS anti-punchthrough region and an ESD double diffused region. Spacer structures are formed around the gate structures. The NMOS region and the ESD protective region are then doped with third dopants, for a n-junction region in the semiconductor substrate uncovered by the gate structures. The PMOS region is doped with fourth dopants for a p-junction region in the semiconductor substrate uncovered by the gate structures. Finally, a thermal process is performed to the semiconductor substrate to activate the first dopants, the second dopants, the third dopants, the fourth dopants.

REFERENCES:
patent: 5481129 (1996-01-01), DeJong et al.
patent: 5897348 (1999-04-01), Wu
Kueing-Long Chen, Effects of Interconnect Process and Snapback Voltage on the ESD Failure Threshold of NMOS Transistors, 1988 EOS, pp. 212-219.
T. Mizuno et al., Hot-Carrier Effects in 0.1.mu.m Gate Length COMS Devices, 1992 IEEE, pp. 695-698.
Takashi Hori, A 0.1-.mu.m COMS Technology with Tilt-Implanted Punchthrough Stopper (TIPS), 1994 IEEE, pp. 75-78.

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