Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Patent
1998-01-08
1999-04-20
Quach, T. N.
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
438655, 438664, 438669, H01L 21336
Patent
active
058952446
ABSTRACT:
The method of the present invention is a method of forming a gate oxide layer on the substrate. An undoped polysilicon layer is formed over the gate oxide layer. Then, a silicon nitride layer is formed over the undoped polysilicon layer. A doped polysilicon layer is formed over the silicon nitride layer. Next, the doped polysilicon layer is patterned to define a gate region. A thermal oxidation is performed on the patterned doped polysilicon gate region to oxidize a portion of the patterned doped polysilicon layer into a thermal oxide film. The thermal oxide film is removed by an etching process. A portion of the first dielectric layer is etched by using the residual doped polysilicon layer as a mask. The undoped polysilicon layer is etched by using the residual doped polysilicon layer and the residual first dielectric layer as a mask. Then, a PSG layer is deposited over the residual nitride layer and the substrate to serve as an ion diffusion source. Subsequently, the PSG layer is etched back to form side-wall spacers. A noble or refractory metal layer is deposited on all areas. Next, a high dose arsenic or phosphorus ion is implanted through the substrate to form first doped regions to serve as source and drain regions of the transistor. Finally, the two-step RTP annealing process is used to form a self-aligned silicided contact nMOSFET.
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Takagi, M.T., et al., "A Novel 0.15 .mu.m CMOS Technology . . . ", IEDM Tech. Digest, 1996, pp. 455-458, Dec. 1996.
Ono, M., et al., "Sub-50 nm gate length n-MOSFETs . . . ", IEDM Tech. Digest, 1993, pp. 119-121, Dec. 1993.
Quach T. N.
Texas Instruments - Acer Incorporated
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