Process to fabricate ultra-short channel MOSFETS with self-align

Details Process to fabricate ultra-short channel MOSFETS with self-align Process to fabricate ultra-short channel MOSFETS with self-align

1999-04-14

2000-04-04

Fahmy, Wael

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

438301, 438305, 438649, H01L 21336

Patent

active

060460903

ABSTRACT:
The method of the present invention includes the steps as followings. At first, a gate oxide layer is formed on the substrate. An undoped polysilicon layer is formed over the gate oxide layer. Then, a first dielectric layer is formed over the undoped polysilicon layer. A second silicon layer is formed over the first dielectric layer. Next, the second silicon layer is patterned to define a gate region. An etching process is performed to the second silicon layer to narrow the gate region. Portions of the first dielectric layer are etched by using the residual second silicon layer as a mask. The undoped polysilicon layer is etched by using the residual second silicon layer and the residual first dielectric layer as mask. Then, a PSG is layer deposited over the residual first dielectric layer and the substrate. Subsequently, the PSG layer is etched back to form side-wall spacers to serve as ion diffusion source. A noble or refractory metal layer is deposited on all area of the substrate. Next, a high dose arsenic or phosphorus ion implantation is performed through the metal layer to form first doped regions to serve as source and drain regions of the transistor. Finally, the two-step RTP annealing process is used to form self-aligned silicided contact of nMOSFETs.

REFERENCES:
patent: 5656519 (1997-08-01), Mogami
patent: 5753557 (1998-05-01), Tseng
patent: 5902125 (1999-05-01), Wu

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