Process technology architecture of embedded DRAM

Details Process technology architecture of embedded DRAM Process technology architecture of embedded DRAM

2000-09-27

2003-07-29

Cao, Phat X. (Department: 2814)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S300000, C257S365000

Reexamination Certificate

active

06600186

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to integrated circuits containing logic circuits and embedded Dynamic Random Access Memory (DRAM). More particularly, this invention relates structures of pass transistors within the embedded DRAM such that the processing of the pass transistor is equivalent to that of transistors that form the logic core.
2. Description of the Related Art
Application Specific Integrated Circuits (ASIC) contain sections of circuitry that implement digital logic, provide peripheral circuits to interface to system function, memory, and analog functions. As DRAM has been embedded into an ASIC, the process for constructing the ASIC has become more complex.
Refer now to
FIGS. 1
a
,
1
b
, and
1
c
for discussion of the structure of an ASIC containing a logic core and an embedded DRAM array.
FIG. 1
b
illustrates an embedded DRAM cell. The embedded DRAM cell has a pass transistor Mp
105
and a cell capacitor C
c
102
. The first plate of the cell capacitor C
c
102
is connected to the drain of the pass transistor Mp
105
. The second plate of the cell capacitor is generally connected to the substrate biasing voltage source Vss. The second plate of the cell capacitor may alternatively be connected to a biasing voltage source that is one half the voltage level of the power supply voltage source V
DD
.
The source of the pass transistor Mp
105
is connected to a bit line voltage generator V
BIT
. The bit line voltage generator V
BIT
generates signals that have the appropriate voltage levels that are used to charge or discharge the cell capacitor C
c
102
. Generally the voltage level of the power supply voltage source V
DD
is used to represent a logical 1 and the ground reference level represents a logical 0.
The gate of the pass transistor Mp
105
is connected to the word line voltage generator V
WORD
. The word line voltage generator V
WORD
activates the pass transistor Mp
105
when brought to a voltage level greater than the threshold voltage level Vt of the pass transistor Mp
105
. If bit line voltage generator V
BIT
and thus the source of the pass transistor Mp
105
is at the voltage level of the power supply voltage source V
DD
, the word line voltage generator has to have a voltage level that is from 1.5-2 times the voltage level of the power supply voltage source.
A basic logic circuit is shown in
FIG. 1
c
. The N-channel MOS transistor M
1
110
and the P-channel MOS transistor M
2
115
are configured as a CMOS inverter. By appropriate placement of additional N-channel and P-channel MOS transistors within the circuit, more complex logic functions can be created. Further, the inverter can be constructed as a driver or receiver within peripheral circuits of the logic core by appropriate design of the transistor parameters and geometry.
The structure of a DRAM cell is shown in
FIG. 1
a
. The pass transistor Mp
105
is formed on the semiconductor substrate
100
by first implanting an N-type material to a lightly doped concentration into the surface of the substrate
100
to form a deep N-well
125
. A P-type material is then implanted into the surface of the semiconductor substrate
100
within the area of the deep N-well
125
to form the P-well
130
. The N-type material is then diffused to highly doped concentration into the P-well
130
to form the source
135
and drain
140
of the pass transistor Mp
105
.
The cell capacitor C
c
120
is then formed by techniques known in the art, such as stacked capacitor or trench capacitor formation.
The transistors M
1
115
and M
2
110
of the logic circuit are formed concurrently with the pass transistor Mp
105
. The N-type material is implanted to the lightly doped concentration to form the N-well
175
. The N-type material is implanted to a highly doped concentration to form the source
155
and drain
160
of the N-channel transistor
110
.
The P-type material is implanted to a highly doped concentration into the surface of the semiconductor substrate
100
to form the source
180
and the drain
185
of the P-channel MOS transistor
115
.
A thin gate oxide is formed on the surface of the semiconductor substrate
100
in the areas
165
and
190
above the channel region between the source
155
and the drain
160
of the N-channel transistor
110
, and the source
180
and the drain
185
of the P-channel transistor
115
.
Since the voltage level of the word line voltage generator V
WORD
is as much as twice the voltage level of the power supply voltage source V
DD
, the gate oxide
145
above the channel between the source
135
and the drain
140
of the pass transistor M
p
105
is deposited as a thick gate oxide to prevent excess stress within the thick gate oxide
145
. Having multiple thicknesses of the gate oxides
145
,
165
and
190
complicates the fabrication process of an ASIC that includes embedded DRAM thus increasing cost. Further, having multiple steps of gate oxide formation causes a higher defect density with the gate oxide.
Typically, the thick oxide is formed to a thickness of from approximately 70 Å to approximately 150 Å, while the thin oxide has a thickness of from approximately 30 Å to approximately 70 Å for the logic circuit and the peripheral circuits. Generally the peripheral circuits have a higher operating voltage, and therefore require the thickness of the thin oxide and the thick oxide to be thicker than that of the logic circuit.
U.S. Pat. No. 5,668,035 (Fang et al.) discusses a method for fabricating an ASIC with an embedded memory array and a logic core. The method is described for forming a thin gate oxide for the logic core, while providing a thicker oxide for the memory cells having a boosted word line architecture. The method avoids applying photoresist directly to the gate oxide, and thereby prevents contamination. A first gate oxide is formed on the device areas on the substrate. A first polysilicon layer is deposited and patterned leaving portions over the memory cell areas. The first gate oxide is removed over the logic core areas, and is replaced by a thinner second gate oxide. A second polysilicon layer is deposited and patterned to remain over the logic core areas. The first and second polysilicon layers, having essentially equal thickness, are coated with an insulating layer. The FET gate electrodes for both the logic and memory cell areas are simultaneously patterned from the first and second polysilicon layers to complete the DRAM structure up to and including the gate electrodes.
U.S. Pat. No. 5,702,988 (Liang) describes a method of forming semiconductor logic devices and memory devices on a single semiconductor substrate. The memory devices that may be formed include nonvolatile memory, DRAM and/or SRAM. The method begins by forming triple-well structure of N-well regions, P-well regions, and P-well in N-well regions on a semiconductor substrate. Field isolation regions are then formed. A cell is formed for each memory device in the memory regions. A channel implant is performed in the substrate for each of the logic and memory devices. A gate and gate oxide is formed individually for each of the logic and memory devices. LDD (Lightly Doped Drain) active regions and heavily doped source/drain regions are formed adjacent to each gate. Additional memory structures are formed, such as a DRAM capacitor. An interlevel dielectric and contact openings therein are formed. One or more metal layers are subsequently deposited over the interlevel dielectric layer and in the openings to make contact to the contact regions.
U.S. Pat. No. 5,712,201 (Lee et al.) teaches a semiconductor fabrication process in which both DRAM and logic device structures are integrated on a single silicon chip. The process features combining process steps for both device types, while using only a single level of polysilicon for both a high capacity DRAM cell, as well as for a CMOS logic core. The high capacity DRAM cell is composed of an overlying polysilicon storage gate structure, a thin dielectric layer, and an un

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