Process sequence and mask layout to reduce junction leakage...

Details Process sequence and mask layout to reduce junction leakage... Process sequence and mask layout to reduce junction leakage...

2007-07-17

2007-07-17

Smith, Zandra V. (Department: 2822)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S216000, C438S218000, C438S585000, C438S287000, C438S294000

Reexamination Certificate

active

10874927

ABSTRACT:
A method of forming a thin gate insulator layer comprises forming an active region surrounded by STI regions; forming a first insulator layer on the active device region; forming a patterned photoresist layer over the first insulator layer and a at least a portion of the STI regions; etching the first insulator layer to expose a portion of the active device region, wherein the photoresist layer substantially protects the STI regions during etching; forming a thin gate insulator layer on the exposed portion of the active device region, wherein said first insulator layer located on a remaining portion of said active device region is converted to a thicker second insulator layer; and forming a conductive gate structure overlying a first portion of the thin gate insulator layer while a second portion of the thin gate insulator layer not covered by the conductive gate structure is removed.

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Wolf et al. “Silicon Processing For The VLSI Era,” vol. 1, Lattice Press, 1986, pp. 198, 384-386, 532-534, 541-542 and 556-557.

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