Process sequence and mask layout to reduce junction leakage...

Details Process sequence and mask layout to reduce junction leakage... Process sequence and mask layout to reduce junction leakage...

2005-02-01

2005-02-01

Gurley, Lynne (Department: 2812)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S216000, C438S218000, C438S283000, C438S287000, C438S294000, C438S424000, C438S585000

Reexamination Certificate

active

06849485

ABSTRACT:
A method of forming a thin silicon dioxide gate insulator layer for use in dual gate insulator device has been developed, featuring a process sequence that results in a reduction of the recessing and notching of surrounding STI regions, and a reduction of silicon damage and device leakage, when compared to counterparts fabricated without the use of this invention. An insulator layer is grown on, and removed via a wet etch procedure, from only the portion of the active device region to be used to accommodate the thin silicon dioxide gate insulator component of the dual gate insulator device. The photolithographic layout and photoresist shape used for removal of these portions of the insulator layer, protect the surrounding STI regions from the wet etch procedure, in addition to leaving insulator layer on portions of the active device region, allowing the underlying portions of the active device region to be protected during a dry etch procedure used to define a conductive gate structure on the thin silicon dioxide gate insulator layer. The thin silicon dioxide gate insulator layer is grown on the portion of active device region previously occupied by the portion of insulator layer removed via the wet etch procedure.

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Wolf et al., “Silicon Processing For The VLSI Era”, vol. 1, Lattice Press, 1986, pp. 198, 384-386, 532-534, 541-542, and 556-557.

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