Semiconductor device manufacturing: process – Coating of substrate containing semiconductor region or of... – Insulative material deposited upon semiconductive substrate
Reexamination Certificate
1998-04-22
2001-03-20
Elms, Richard (Department: 2824)
Semiconductor device manufacturing: process
Coating of substrate containing semiconductor region or of...
Insulative material deposited upon semiconductive substrate
C438S411000, C438S421000, C438S422000
Reexamination Certificate
active
06204200
ABSTRACT:
FIELD OF THE INVENTION
The invention is generally related to the field of interconnect layers for semiconductor devices and more specifically to forming airgaps between interconnect lines to reduce capacitance.
BACKGROUND OF THE INVENTION
For current integrated circuit (IC) technology, the speed limiting factor is no longer the transistor gate delay, but the RC delays associated with the interconnects. For this reason, a great deal of work has been done on developing new low dielectric constant materials to reduce interconnect capacitance. Some of these dielectrics include fluorinated silicon dioxide, polymers, and xerogels. However, these material currently pose numerous reliability, manufacturability, and integration issues. Some of these include 1) mechanical strength; 2) dimensional stability; 3) thermal stability; 4) ease of pattern and etch; 5) thermal conductivity; and 6) chemical-mechanical polish (CMP) compatibility. Most low dielectric constant materials under investigation are, as currently developed, inferior to the currently used intermetal dielectric material, silicon dioxide, in most if not all of the above properties.
Also, as IC's continue to scale, the intralevel line-to-line capacitance increasingly dominates over the interlevel capacitance. Thus, it becomes increasingly important that the low dielectric constant material be used between adjacent metal lines and less so between metal levels. Moreover, since tighter metal spacings have increased capacitance, the need for low dielectric constant material there is greater.
SUMMARY OF THE INVENTION
A process for forming controlled airgaps between metal lines is disclosed herein. A two-step high density plasma (HDP) chemical vapor deposition (CVD) process is used to form the silicon dioxide dielectric layer with the controlled airgaps. The first step involves a high gas flow and low substrate bias conditions to deposit silicon dioxide with a high deposition to sputter etch ratio. The second step uses a low gas flow and high substrate bias condition to increase the sputter component of the deposition.
An advantage of the invention is providing a low capacitance intrametal dielectric that can be used with current backend processes.
Another advantage of the invention is providing a interlevel dielectric that maintains the mechanical stability, thermal conductivity, and thermal stability of current processes.
Another advantage of the invention is providing a interlevel dielectric that does not cause outgassing as many of the proposed low K materials do.
Another advantage of the invention is providing a interlevel dielectric that is compatible with scaling trends (i.e., airgaps tend to form more easily in tighter metal spaces where capacitance reduction is most required) .
These and other advantages will be apparent to those of ordinary skill in the art having reference to the specification in conjunction with the drawings.
REFERENCES:
patent: 5324683 (1994-06-01), Fitch et al.
patent: 5679606 (1997-10-01), Wang et al.
patent: 5728631 (1998-03-01), Wang
patent: 5837618 (1998-11-01), Avanzino et al.
patent: 6031286 (2000-02-01), Levine et al.
Wolf and Tauber, “Silicon Processing for the VLSI Era”, V1—Process Technology, chp. 6, 1986.
List Richard S.
Nag Somnath S.
Shieh Benjamin P.
Brady III W. James
Elms Richard
Garner Jacqueline J.
Telecky , Jr. Frederick J.
Texas Instruments Incorporated
LandOfFree
Process scheme to form controlled airgaps between... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Process scheme to form controlled airgaps between..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Process scheme to form controlled airgaps between... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2436643