Process of planarizing crown capacitor for integrated circuit

Details Process of planarizing crown capacitor for integrated circuit Process of planarizing crown capacitor for integrated circuit

1999-09-08

2001-01-23

Bowers, Charles (Department: 2813)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S279000, C438S253000, C438S396000

Reexamination Certificate

active

06177307

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention generally relates to semiconductor integrated circuit fabrication. More particularly, the present invention relates to a process of planarizing crown capacitors for integrated circuitry.
2. Description of the Related Art
The crown capacitor has been widely applied to the dynamic random access memory (DRAM), for providing sufficient capacitance as semiconductor devices scale down in size. In the conventional process of manufacturing the crown capacitor, the bottom electrode is configured with an inner sidewall and outer sidewall to be exposed, thus raising a planarization issue. To overcome this problem, one approach is to apply an additional chemical mechanical polishing (CMP) process after the inner sidewall and the outer sidewall of the bottom electrode has been exposed; the other approach makes use of a photoresist layer, formed through an extra photolithography process, to overlie the peripheral circuit area while insulating material is filled onto the exposed inner sidewall and outer sidewall in the cell area.
SUMMARY OF THE INVENTION
Therefore, it is an object of the present invention to provide a process for planarizing crown capacitors without an additional CMP step after the inner sidewall and the outer sidewall of the bottom electrode has been exposed.
It is another object of the present invention to provide a process for planarizing crown capacitors without an extra photolithography step to block the peripheral circuit area.
For achieving the above-identified objects, the present invention provides a method for fabricating an integrated circuit having a cell area and a peripheral circuit area in a semiconductor substrate. First, a memory device and a transistor are formed within the cell area and the peripheral circuit area, respectively, wherein the memory device has a doped region formed in the semiconductor substrate. Then, a first insulating layer is formed to overlie the cell area and the peripheral circuit area, and thereafter patterned to be a trench over the doped region and a recess in the peripheral circuit area. Next, the first insulating layer is patterned through the trench to form a contact window, and a landing plug is filled into the contact window in contact with the doped region. Subsequently, a second insulating layer and a third insulating layer are sequentially formed to overlie the cell area and the peripheral circuit area, and then patterned to form an opening over the doped region. Next, a first conductive layer is formed on the bottom and sidewall of the opening in contact with the landing plug. Then, the third insulating layer in the cell area is removed by a planarization process, and the second insulating layer in the cell area is thereafter removed. Finally, a dielectric layer and a second conductive layer are sequentially formed over the first conductive layer.


REFERENCES:
patent: 5858831 (1999-01-01), Sung
patent: 6010933 (2000-01-01), Cherng
patent: 6022776 (2000-02-01), Lien et al.
patent: 6077738 (2000-06-01), Lee et al.
patent: 6077742 (2000-06-01), Chen et al.
patent: 6121082 (2000-09-01), Linliu et al.

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