Semiconductor device manufacturing: process – Coating of substrate containing semiconductor region or of... – By reaction with substrate
Reexamination Certificate
1995-08-14
2001-09-18
Bowers, Charles (Department: 2813)
Semiconductor device manufacturing: process
Coating of substrate containing semiconductor region or of...
By reaction with substrate
Reexamination Certificate
active
06291366
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a process of manufacturing a semiconductor device.
Liquid crystal display devices of active-matrix type use a so-called thin film transistor (TFT) wherein an insulating-gate field effect transistor (MIS (metal-insulator-semiconductor) transistor) is fabricated on a thin film semiconductor layer as a switching device. Inasmuch as the TFT is formed on a substrate made of a proper material, such as a borosilicate glass or plastic substrate having a low melting point or low heat-resisting property, the TFT, accordingly, the gate insulating film thereof is formed at a low temperature. The gate insulating film is formed by plasma CVD (chemical vapor deposition) wherein a substrate temperature used when the insulating gate film is formed ranges from 600 to 300° C.
As is well-known, if a film-forming temperature, i.e., substrate temperature is lowered when the gate insulating film is formed, then it becomes difficult to obtain a MIS transistor having a desired characteristic.
For example, an n-channel MIS transistor is operated in a depletion-type transistor. Moreover, a p-channel MIS transistor has a problem that a threshold voltage V
th
increases so that the p-channel MIS transistor cannot be energized even on application of a predetermined negative voltage. Thus, a circuit using an n-channel or p-channel MIS transistor cannot be formed as an integrated circuit satisfactorily.
This phenomenon occurs due to a positive electric charge caused by a defect in atomic bonding or impurity in the gate insulating film. The positive electric charge is caused by a so-called dangling bond of Si (silicon) of SiO
2
, for example. When the positive electric charge exists near the interface between the gate insulating film and the semiconductor, a flat-band voltage is shifted (moved), resulting in the n-channel MIS transistor being operated in the depletion type transistor or the ON-voltage of the p-channel MIS transistor being increased.
When an operation voltage of the MIS transistor is relatively large, e.g., about ±20V, a flat-band voltage shift of about +4V is allowable. However, this flat-band voltage shift becomes fatal to an increasing demand in which the MIS transistor can be driven by a low voltage, e.g., ±5V.
As a method of solving the aforesaid problem, there is proposed a post-anneal wherein a defect can be compensated by heat treatment in an oxygen atmosphere such as the air after the gate insulating film has been formed. The post-anneal (including a hydrogen plasma treatment) might be a reducing anneal containing hydrogen gas, an air anneal or the like. The reducing anneal needs an annealing at a high temperature in excess of 400° C. According to any one of these anneals, a flat-band voltage shift increases depending on a film quality of the insulating film. Then, effects of the air anneal are fluctuated depending on the season, which brings about a problem in actual practice.
SUMMARY OF THE INVENTION
In view of the aforesaid aspect, it is an object of the present invention to provide a process of manufacturing a semiconductor device in which a quality of semiconductor can be improved and a desired semiconductor device can be obtained stably.
It is another object of the present invention to provide a process of manufacturing a semiconductor device in which the above-mentioned flat-band shift can be improved.
According to an aspect of the present invention, there is provided a process of manufacturing a semiconductor device. The manufacturing process comprises the steps of annealing a semiconductor at a temperature ranging from 20 to 400° C. in the atmosphere containing a gas of water with a partial pressure ranging from 1 Torr to a saturated vapor pressure for an annealing time from 15 seconds to 20 hours, and reforming at least one of the semiconductor or an insulating film.
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Hara Masaki
Sameshima Toshiyuki
Sano Naoki
Sekiya Mitsunobu
Bowers Charles
Sonnenschein Nath & Rosenthal
Sony Corporation
Thompson Craig
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