Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2000-09-22
2001-07-03
Tsai, Jey (Department: 2812)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S244000
Reexamination Certificate
active
06255158
ABSTRACT:
TECHNICAL FIELD
The present invention relates generally to a dynamic random access memory (DRAM) device and, more particularly, to a vertical DRAM device having a wordline self-aligned to a storage trench.
BACKGROUND OF THE INVENTION
In the semiconductor industry, there is an ever-increasing desire to increase memory density and performance. These goals are often achieved by scaling dynamic random access memory (DRAW devices to smaller dimensions and operating voltages.
Vertical DRAM devices use a trench to form both a signal storage node and a signal transfer device. Vertical DRAM devices have been proposed to increase memory density because they decouple the length of the vertical signal transfer device channel from the minimum feature size. This configuration allows longer channel lengths without a proportional decrease in memory density. Channel length may then be properly scaled relative to gate oxide thickness and relative to junction depth to reduce channel doping, minimize junction leakage, and increase retention times.
FIG. 1
shows a partial cross-sectional view of a vertical DRAM device or cell
100
formed in a substrate
101
(typically P-silicon). The DRAM cell
100
is formed using a trench (DT or deep trench) having a sidewall
122
. The DRAM cell
100
includes a signal storage node (partially shown)
102
which includes a storage node conductor
104
(typically N+ polysilicon) and a collar oxide
106
. The signal transfer device of the DRAM cell
100
includes a first diffusion region
108
, a second diffusion region
110
(typically N+ silicon), a channel region
112
, a gate insulator
114
, and a gate conductor
116
(typically N+ polysilicon).
The gate conductor
116
is coupled to the wordline
118
. The wordline
118
comprises an N+ polysilicon lower layer
118
A, a WSi
x
middle layer
118
B, and a nitride layer
118
C. The second diffusion region
110
is covered by a nitride layer
120
. The storage node conductor
104
is covered by a trench-top oxide (TTO)
123
. A shallow trench isolation (STI) region
128
is formed to provide isolation for DRAM device
100
.
The trench sidewall
122
of the DRAM cell
100
is a distance W from the sidewall
124
of the trench of an adjacent DRAM cell. For DRAM cells
100
occupying a 5F
2
surface area of the substrate
101
, where F is the minimum feature size, the distance W between adjacent trench sidewalls may be 2F. With a trench-to-trench distance W of 2F, a wordline
118
can overlap past the sidewall
122
of the trench by a distance of 0.5F. This configuration allows adequate overlap of the gate conductor
116
by wordline
118
even in the worst case of misalignment when DT and wordline bias are under control. DRAM cell density on a wafer may be increased by decreasing the trench-to-trench spacing W. As trench-to-trench spacing W is reduced below 2F, the probability that the wordline conductor will not overlap the trench edge increases because the layed out overlap of the wordline to the trench is reduced below 0.5F while the alignment tolerance remains constant.
DRAM cell
100
in
FIG. 1
has a wordline
118
which does not completely overlap the trench sidewall
122
. This incomplete overlap causes the etch used to form the wordline
118
to cut into the underlying gate conductor
116
as illustrated by the gate conductor over-etch
105
. Over-etch
105
may result in damage to the gate insulator
114
and a failure of the gate conductor
116
to overlap the second diffusion region
110
.
To overcome the shortcomings of conventional DRAM devices, a new vertical DRAM device is provided. An object of the present invention is to provide a vertical DRAM device that has a wordline conductor self-aligned to the sidewall of the trench. A related object is to provide a process of manufacturing such a vertical DRAM device. Another object is to provide a pair of vertical DRAM devices each having a respective wordline and each formed using a respective trench in which the distance between the respective trenches equals the distance between respective wordlines. It is still another object to provide a vertical DRAM device having a wordline positioned above the surface of the substrate.
SUMMARY OF THE INVENTION
To achieve these and other objects, and in view of its purposes, the present invention provides a dynamic random access memory device formed in a substrate. The substrate has a top surface and has a trench having a sidewall formed in the substrate. A signal storage node is formed using a bottom portion of the trench and a signal transfer device is formed using an upper portion of the trench. The signal transfer device includes a first diffusion region coupled to the signal storage node and extending from the sidewall of the trench into the substrate, a second diffusion region formed in the substrate adjacent to the top surface of the substrate and adjacent to the sidewall of the trench, a channel region extending along the sidewall of the trench between the first diffusion region and the second diffusion region, a gate insulator formed along the sidewall of the trench extending from the first diffusion region to the second diffusion region, a gate conductor filling the trench and having a top surface, and a wordline having a bottom adjacent the top surface of the gate conductor and a side aligned with the sidewall of the trench.
It is to be understood that both the foregoing general description and the following detailed description are exemplary, but are not restrictive, of the invention.
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Furukawa Toshiharu
Gruening Ulrike
Horak David V.
Mandelman Jack A.
Radens Carl J.
International Business Machines - Corporation
Li, Pat. Agent Todd M. C.
Ratner & Prestia
Tsai Jey
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