Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2001-02-01
2003-12-02
Fourson, George (Department: 2823)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S285000, C438S589000
Reexamination Certificate
active
06656802
ABSTRACT:
The invention relates to a process of manufacturing a semiconductor device including a buried channel field effect transistor comprising, for realizing said field effect transistor, steps of forming a stacked arrangement of layers on a substrate including an active layer, forming a recess in said active layer, called gate recess, for constituting a channel between source and drain electrodes, and forming a gate electrode which is in contact with the active layer in said gate recess.
The invention finds its application for example in the manufacture of microwave frequency circuits which are monolithically integrated in a III-V semiconductor material technology (MMICs).
A process for manufacturing a field effect transistor with buried channel is known from the patent EP 0 690 506. This process comprises steps of manufacturing both a N-OFF and a N-ON transistors at the same time, with a recessed gate. For manufacturing said transistors, these steps comprise depositing, on a substrate, an active layer of GaAlAs and a cap layer of GaAs. The active layer has a non-zero aluminum content while the cap-layer does not contain aluminum. Ohmic contacts for the source and drain electrodes are first formed. Then, a first photo-resist layer is deposited on the cap layer, covering the source and drain electrodes. Gate openings for forming gate contacts are carried out in said first photoresist layer. Performing the gate recesses and the gate electrodes comprise: etching the cap layer using a plasma of a fluorine compound, through the photo-resist gate openings, until a stopper layer is formed at the upper surface of the active layer by formation of aluminum fluoride; elimination of the stopper layer; etching the active layer, for forming a first part of the gate recess of the enhancement transistor, during which, the depletion transistor is covered by a protective layer; then said protective layer is eliminated and the two gate recesses are completed down to the bottom level corresponding to the N-OFF and the N-ON transistors to be formed; and depositing in the gate recesses a metal material for forming the gates having lengths equal to the widths of the photo-resist gate openings. During this process, the openings formed in the semiconductor layers are made larger than the photoresist gate openings by using etching techniques that perform under-etching.
Several field effect transistor types exist at the moment, among them transistors which are normally conducting (N-ON) when the gate is at the same potential as the source and which are pinched off through depletion when the potential of the gate is more negative than that of the source, and transistors which are normally pinched off (N-OFF) when the gate is at the same potential as the source and which are rendered conducting by enhancement when the potential of the gate becomes more positive than that of the source. In these field effect transistors, the active layer below the gate electrode has a given thickness, which is smaller in the enhancement-type transistor than in the depletion-type transistor. In integrated semiconductor devices realized from III-V materials, such as GaAs compounds, amplifier transistors may be realized by enhancement-type transistors, while the charges are realized in active form by depletion-type transistors.
In vacuum or air, for example, the doped GaAs material of the active layer has a surface tension which is determined by the Fermi-level—the surface states being situated at the center of the forbidden band—and which is of the order of −0.5 V. The result is that the active layer is normally depleted on either side of the gate contact, in the so-called access regions, which are accordingly non-conducting in the normal state. In the depletion-type transistor (N-ON), this surface effect is less unfavorable because the active layer is comparatively thick below the gate, which allows the transistor to be normally conducting up to the moment where an application of a negative gate voltage depletes the active layer also below the gate itself, rendering the transistor completely non-conducting. In the enhancement-type transistor (N-OFF), where the active layer below the gate is thinner, this surface effect is always very unfavorable because the depleted access regions occupy non-negligible portions of the active layer with respect to the thickness on either side of the gate. These depleted access regions are not rendered conducting by the application of a positive gate voltage with respect to the source, which enhances the active layer practically only below the gate, and accordingly the number of electrons generated is lower than expected. The saturation velocity is in addition reduced. Accordingly, the saturation current, which depends on the number of generated electrons and on the saturation velocity, is reduced thereby.
The cited document does not present a solution to the problem posed by these depleted access regions.
This problem particularly occurs when realizing transistors provided with a recessed gate having a very small gate length inferior to 0.2 &mgr;m, as currently needed in the field of semiconductor devices, and having subsequently very narrow access regions, for example of the order of magnitude of the gate length. This problem is especially acute in the case of enhancement-type transistors (N-OFF). For example, this problem occurs when forming a transistor having a gate whose length is as small as possible, typically 0.1 &mgr;m, which is disposed in a recess whose total width is as small as possible, typically 0.25 to 0.30 &mgr;m. In this case, the access region total width is of the order of 0.15 &mgr;m to 0.20 &mgr;m. This problem, called Kink effect, is revealed by the formation of a discontinuity of the slope of the saturation current characteristic. This characteristic is a curve of the drain-source current in function of the drain-source voltage for a given gate-source voltage. So, considering a N-OFF transistor having a pinch-off voltage between −0.1 and +0.4V, when the drain-source voltage is less than 3 V, the saturation current characteristic shows a first slope that is not steep enough. When the drain-source voltage reaches values superior to 3V, said saturation current shows a second different slope that is steeper. Now, it may be needed to dispose of a transistor having such small gate length and working with a drain-source voltage in a range of 0.5V to 4V or 5V. The discontinuity in the saturation current characteristic slope shows that it is not possible to use such recessed gate transistor having such a small gate length and narrow access regions and working properly in said range of drain-source voltage.
An other problem lies in the fact that a transistor having such small dimensions is very difficult to manufacture. So, the manufacturing process must be very simple, involving as few steps as possible and as few layers as possible, which is by itself difficult.
The present invention has for its object to provide a semiconductor device including a field effect transistor with a one-recessed gate having a gate length inferior to 0.21&mgr; and an improved saturation current characteristic, while using a process of fabrication involving very simple techniques, for providing this semiconductor device in large quantities at low cost, and accurate performances. The present invention has also for its object to provide a semiconductor device including such a field effect transistor, which may be used in low noise and high bit rate applications.
A process of manufacturing a semiconductor device including such a transistor is claimed in claim
1
. According to the invention, it has been found that the Kink effect problem of the discontinuity in the saturation current characteristic curve occurs when the gate length is inferior to 0.2 &mgr;m in a transistor and when the access region total width is too large with respect to the gate length. The present process permits of solving this problem and is available for obtaining either an enhancement or a depletion-type transistor
Fourson George
Koninklijke Philps Electronics N.V.
Toledo Fernando
Wagner Aaron
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