Process of manufacturing a dual gate CMOS transistor

Details Process of manufacturing a dual gate CMOS transistor Process of manufacturing a dual gate CMOS transistor

2001-04-10

2003-04-22

Elms, Richard (Department: 2824)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S222000, C438S224000, C257S371000

Reexamination Certificate

active

06551871

ABSTRACT:

CROSS-REFERENCE TO RELATED APPLICATION
This application is related to Japanese application No. 2000-148053 filed on May 19, 2000, whose priority is claimed under 35 USC §119, the disclosure of which is incorporated by reference in its entirety.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a process of manufacturing a semiconductor device. In particular, it relates to a process of manufacturing a semiconductor device having a miniaturized dual gate CMOS transistor.
2. Description of Related Art
In a trend to miniaturization of MOS transistors due to development of semiconductor processing techniques, a dual gate CMOS transistor has generally been applied since it inhibits short channel effect and reduces OFF current. The dual gate CMOS transistor utilizes an n-type polysilicon file and a p-type polysilicon film as gate electrodes of an nMOS transistor and a pMOS transistor, respectively.
In the dual gate CMOS transistor, the gate electrode is implanted with n- or p-type impurities by ion implantation for forming a shallow junction as a source/drain region. Accordingly, the impurities are not sufficiently introduced into the neighborhood of a gate insulating film and depletion occurs in the gate electrode, which deteriorates transistor properties.
Further, in the formation of the pMOS transistor, BF
2
ions are generally implanted to form a source/drain region of a shallow junction. Boron ions introduced into the gate electrode tends to cause enhanced diffusion in the gate insulating film due to the presence of fluorine and penetrates the gate insulating film to diffuse into a channel region, which varies a threshold value of the transistor. The current MOS transistor utilizes a gate insulating film which is as very thin as several tens of Å and it tends to be further thinned due to the miniaturization of the MOS transistor. Therefore it is considered that the penetration of boron ions through the gate insulating film will occur more remarkably.
Japanese Unexamined Patent Publication No. HEI 6 (1994)-310666 has proposed a method of preventing the depletion of the gate electrode as described below.
As shown in FIG.
3
(
a
), a p-well
52
a
and an n-well
52
b
are formed in a nMOS region and an pMOS region, respectively by ion implantation in a semiconductor substrate
50
provided with device isolation films
51
.
Then, a gate insulating film
53
and a silicon film
54
are formed on the semiconductor substrate
50
as shown in FIG.
3
(
b
) and n- and p-type impurities are implanted to the nMOS region and the pMOS region, respectively. The obtained semiconductor substrate is then annealed to form an n-type polysilicon film
54
a
and a p-type polysilicon film
54
b
as shown in FIG.
3
(
c
).
Further, the n-type polysilicon film
54
a
and the p-type polysilicon film
54
b
are patterned into a desired configuration to form gate electrodes as shown in FIG.
3
(
d
). Ion implantation is then performed to form LDD regions
56
a
and
56
b
in the nMOS region and the pMOS region, respectively. Then an insulating film is deposited on the entire surface of the semiconductor substrate
50
and etched back to form sidewall spacers
55
onto the gate electrodes.
With the sidewall spacers
55
and the gate electrodes as a mask, ion implantation is carried out to the nMOS region and the pMOS region, respectively, and annealing is performed to form source/drain regions
57
a
and
57
b
as shown in FIG.
3
(
e
).
Thereafter, a titanium film is formed on the resulting semiconductor substrate
50
and thermally treated to provide a titanium silicide film
58
on the source/drain regions
57
a
and
57
b
and the gate electrodes. An interlayer insulating film
59
and contact holes are provided and then contact plugs
60
and a wiring layer
61
are formed by a wiring process.
In summary, a resist mask is formed in advance by photolithography before the formation of the gate electrode, with which suitable ions are implanted to the polysilicon films in the nMOS region and the pMOS region, respectively, and then annealed to obtain the nMOS transistor and the pMOS transistor.
Through these steps, impurities are sufficiently introduced into the gate electrodes in the neighborhood of the gate insulating film and the depletion of the gate electrodes is prevented.
In the above-mentioned method, however, an additional photolithography step has to be carried out for ion implantation to the gate electrodes. Further, annealing has to be carried out for a relatively long period or in plural times in order to diffuse the impurities from the surface of the gate electrode to an interface between the gate electrode and the gate insulating film. Accordingly, manufacturing steps are increased and lengthened, which leads to an increase of production costs.
The depletion of the gate electrode can be prevented by thinning the polysilicon film consisting the gate electrode or increasing a dose and an acceleration energy for ion implantation for forming the source/drain region. However, the former may increase the amount of boron ions penetrating the gate insulating film or deteriorate the gate insulating film due to stress applied by a salicide step. The latter may lead short channel effect and increase junction leak current caused by defects of the semiconductor substrate due to ion implantation as well as promote the penetration of boron ions through the gate insulating film particularly in the pMOS transistor.
Further, Japanese Unexamined Patent Publication No. HEI 11(1999)-307765 has proposed a method of avoiding multiplication of the photolithography steps. According to this method, a polysilicon film of large particle diameter doped with phosphorus is formed on the entire surface of a semiconductor substrate and a non-doped polysilicon film is formed thereon. These polysilicon films are patterned to form gate electrodes. Thereafter, at the ion implantation for forming a source/drain region, phosphorus previously doped as n-type impurities are compensated by p-type impurities of high concentration to provide a p-type gate electrode in the pMOS region.
However, when the p-type impurities are implanted in a dose capable of preventing the depletion of the gate electrode, inhibition of short channel effect becomes insufficient as this method involves eliminating the n-type impurities and giving p-type conductivity to the gate electrode by the ion implantation for forming the source/drain region.
This method may prevent the depletion of the gate electrode by annealing at high temperature and/or for a long time to activate the impurities. However, the method is still problematic in that the impurity diffusion in the source/drain region is enhanced, and short channel effect and penetration of boron ions through the gate insulating film in the pMOS transistor remarkably occur.
The penetration of boron ions through the gate insulating film can be inhibited by performing the ion implantation for forming the source/drain region with boron ions free from fluorine. However, the use of boron ions makes the formation of a shallow source/drain region difficult, so that short channel effect cannot be prevented and OFF current increases.
It may be possible to inhibit the penetration of boron ions by using amorphous silicon as a gate electrode material instead of polysilicon, utilizing polysilicon of large particle diameter as proposed in Japanese Unexamined Patent Publication No. HEI 11(1999)-297852, or providing an extremely thin insulating film at an interface within a multilayered silicon film. However, impurity diffusion in the gate electrode is hindered and therefore the depletion of the gate electrode easily occurs.
Thus, in the present situation, there has not been established yet a method which allows all the requirements for prevention of short channel effect, reduction of OFF current, inhibition of depletion of the gate electrode and prevention of penetration of boron ions through the gate insulating film in a miniaturized dual gate CMOS transistor.
SUMMARY OF THE I

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