Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2000-04-12
2001-09-25
Smith, Matthew (Department: 2825)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S257000, C438S268000, C438S273000, C438S279000, C438S302000, C438S324000
Reexamination Certificate
active
06294431
ABSTRACT:
TECHNICAL FIELD
The present invention relates to a process of manufacture of a non-volatile memory, particularly of an EPROM or Flash EPROM memory type in NOR type configuration, and, more particularly, to a process assuring the electric continuity of the common source lines present in the matrix of memory cells.
BACKGROUND OF THE INVENTION
In matrixes of self-aligned cells, present in EPROM or Flash EPROM non-volatile memories, a problem is presented by the definition of common source lines in the active area zones. With the use of sufficiently large memory cells, these lines are defined together with the definition of the active area and are subsequently doped. With the miniaturization of the cells, the source lines are instead defined in a step following the definition of the active area and the gate, through a dedicated mask. In fact, in a conventional process for the realization of a matrix of non-volatile memory cells, for instance EPROM type, after having defined the active area zones, covered by a thin layer of oxide (gate oxide), and the field oxide zones, a first layer of polycrystalline silicon or polysilicon is deposited on the whole surface of the silicon wafer and therefore, through an opportune mask, the first polysilicon layer is etched for forming regions of lower polysilicon along the active areas, where the bits line will be formed.
In a following step there is provided the deposition of an intermediate dielectric layer (for instance ONO) on the whole surface of the wafer and therefore the definition, through the deposition of a second polysilicon layer and a subsequent selective etching, of seconds strips of upper polysilicon, superimposed and transversal to the aforesaid regions of lower polysilicon, that constitute the words line. The several intersections between each word line and each bit line form the memory cells. In a following step, a second mask is used for allowing the execution of a source implant. According to a process largely used for the production of EPROM or Flash EPROM type memory cells, defined SAS (Self-Aligned Source), it is initially foreseen a coverage of the drain zones of the cell through a mask shaped as rectangular strips that are aligned to the middle of the gate strips. Subsequently the thick oxide present in the zones between the gate strips not covered by the mask is etched, for the removal of the thick oxide. A step of ionic implant of a dopant in the silicon wafer is subsequently effected for the formation of the regions of source and drain of the matrix of memory cells and to guarantee an electric continuity of the source lines.
At this point, a thermal treatment of reoxidation is performed.
Subsequently a dielectric layer is deposited, for instance TEOS, which uniformly covers the structure. Such dielectric layer is etched to define insulating sidewall spacers, adjacent to every gate region. A further step of implanting of dopant of the same type follows, both for the source lines and for the drain lines.
A different technique used for getting electrically continuous common source lines is the “STI” (Shallow Trench Isolation) technique. During the step of the previously-described process for the manufacture of a matrix of non-volatile memory, which foresees a second etching of the first polysilicon layer, the active area zones no more covered by the gate oxide or by the first polysilicon layer are also etched, and excavations are therefore formed in the uncovered silicon. The STI technique foresees, in a process step preceding the formation of such excavations, the introduction of a dopant in the zones wherein such excavations will be formed, creating highly-doped regions deeper than the excavations so as to decrease the resistance of the common source lines of the matrix of non-volatile self-aligned memory cells. Such excavations will be subsequently filled with oxide.
The SAS process is particularly onerous and inherently introduces several problems. In fact it is necessary to perform an etching for the removal of the field oxide that leaves the uncovered zones of silicon and polysilicon unaffected, nevertheless it is possible that the edge of the gate oxide of some cells is also deformed provoking problems of reliability of the cell.
The STI process foresees the realization of an electric continuity of the common source lines through the presence of doped zones, with the same type of dopant of the source regions that cover the excavations. Nevertheless, such zones can introduce some pinching, due to a non-uniform doping, that cause a discontinuity of the source lines creating zones of high resistance.
SUMMARY OF THE INVENTION
In view of the state of the art described, the disclosed embodiments of the present invention provide a process of manufacture that guarantees an electric continuity of the source lines of a matrix of non-volatile self-aligned memory cells.
According to the embodiments of the present invention, such object is reached through a process for the manufacture of a non-volatile memory with memory cells arranged in lines and columns in a matrix structure, with source lines extending parallel and intercalate to said lines, said source lines formed by active regions intercalated to field oxide zones, said process comprising steps for the definition of active areas of said columns of said matrix of non-volatile memory cells and the definition of said field oxide zones, subsequent steps for the definition of the lines of said matrix of non-volatile memory cells, a following step for the definition of said source lines. The process is further characterized by the fact that in the step for the definition of the source lines, a process step comprising a selective introduction of dopant is accomplished to form a high dopant concentration buried layer of silicon, said buried silicon layer being formed to such a depth to coincide with the regions of silicon underlying the field oxide zones, a subsequent introduction of dopant in said active regions of the source lines to superficially contact said buried silicon layer.
In accordance with the disclosed embodiments of the present invention, it is possible to realize through an implant of dopant of source in the regions underlying the zones of thick oxide a buried region having an electric continuity between the surface of the silicon with the source lines.
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Bez Roberto
Riva Caterina
Servalli Giorgio
Galanthay Theodore E.
Seed IP Law Group PLLC
Smith Matthew
STMicroelectronics S.r.l.
Tarleton E. Russell
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