Process of making unlanded vias

Details Process of making unlanded vias Process of making unlanded vias

1997-12-30

1999-11-02

Utech, Benjamin

Semiconductor device manufacturing: process

Chemical etching

Combined with coating step

438706, 438710, H01L 2102

Patent

active

059769840

ABSTRACT:
A method of making vias in a semiconductor IC device having adequate contact to the surface of the interconnects and without inadequate landing is disclosed. The method has interconnects formed in a metal layer on the substrate of the IC device, and a first dielectric layer is formed covering the surface of the interconnects. An etch-stopping layer is then formed on top of the first dielectric layer, followed by the formation of a second dielectric layer on top of the etch-stopping layer. A photoresist layer then covers the second dielectric layer and reveals the surface regions of the second dielectric layer designated for the formation of the vias. A main etching procedure is then performed to etch into the second dielectric layer down to the surface of the etch-stopping layer, thereby forming the first section of the vias. An over-etching procedure is then implemented to strip off the etch-stopping layer and further etches into the first dielectric layer and the etching is then stopped when the surface of the interconnects are revealed to conclude the formation of the vias.

REFERENCES:
patent: 5726100 (1998-03-01), Givens
patent: 5728628 (1998-03-01), Havemann
patent: 5854131 (1998-12-01), Dawson et al.

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