Process of making carrier substrate and semiconductor device

Semiconductor device manufacturing: process – Chemical etching – Combined with coating step

Reexamination Certificate

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C257S784000

Reexamination Certificate

active

06423643

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device, a process for producing the same, a carrier substrate and a process for producing the same.
2. Description of the Related Art
As small-sized electronic equipments, such as mobile phones or others, have been come into wide use, there has been a demand for minimizing the size and cutting the production cost of semiconductor devices to be installed in such electronic equipments. A conventional semiconductor device, wherein a semiconductor chip mounted onto a lead frame is resin-shielded, has a problem in that an area extending between inner and outer leads or a mounting area is relatively large. Further, in a BGA (ball grid array) type semiconductor device, there is another problem in that the production cost is high because it necessitates a substrate for mounting a semiconductor chip.
To minimize a size of a semiconductor device and to reduce a mounting area therefor, as well as to cut the production cost, a semiconductor device has been proposed, for example, in Japanese Unexamined Patent Publication (Kokai) No. 9-162348. The semiconductor device disclosed in Kokai No. 9-162348 includes a semiconductor chip mounted onto a chip-cementing resin, a resin package in which the semiconductor chip is shielded with epoxy resin, and a metallic film covering a resinous projection formed on a mounting surface of the resin package, which metallic film is electrically connected to an electrode section of the semiconductor chip by wire-bonding. This semiconductor device is advantageous in that inner and outer leads are unnecessary, contrary to the case wherein a lead frame is used, no substrate is necessary for mounting the semiconductor chip as in the BGA type packages, and the metallic film facilitates heat dissipation as well as eases the mounting operation of the chip onto the substrate because the metallic film has the same function as the connector terminals.
In the above-mentioned semiconductor device of a type wherein a high-frequency semiconductor chip is mounted, the mounting part metallic film on which the semiconductor chip is mounted is preferably used as a ground terminal for preventing noise from entering so that the electric properties are stabilized. Accordingly, it is necessary to electrically connect the ground terminal to the mounting part metallic film.
For example, in a semiconductor device
51
shown in
FIG. 6
, a mounting part metallic film
53
on which a semiconductor chip
52
is mounted and a connector part metallic film
54
electrically connected to the semiconductor chip
52
are partially extended at the side of the mounting surface. A ground connector part
55
is extended outward from a peripheral edge of the mounting part metallic film
53
. A ground electrode of the semiconductor chip
52
and the ground connector part
55
are electrically connected to each other with a wire
56
, and a signal electrode and the connector part metallic film
54
are electrically connected to each other with a wire
58
.
To design the mounting part metallic film
53
as compactly as possible and to make a length of the wire
56
as short as possible, the ground connector part
55
is preferably provided as close as possible to the semiconductor chip
52
. Thereby, there has been a demand for forming the mounting part metallic film
53
in a stepwise configuration. For forming the mounting part metallic film
53
in a stepwise configuration, a process for producing a carrier substrate for the production of the semiconductor device
51
will be described with reference to FIGS.
7
(
a
) to
7
(
h
),
8
(
a
) and
8
(
b
). In this regard, a process for forming the mounting part metallic film
53
will mainly be explained, while avoiding the illustration of the connector part metallic film
54
in FIGS.
7
(
a
) to
7
(
b
).
In FIG.
7
(
a
), an etching resist (photosensitive resist)
61
is coated on the respective surfaces of a metallic substrate
60
, such as a copper plate. Then, as shown in FIG.
7
(
b
), the exposure and development are carried out while overlaying a photo-mask on the etching resist to result in a pattern
62
having a central vacant space of a required size (see FIG.
8
(
a
)). Thereafter, as shown in FIG.
7
(
c
), a first half etching is carried out (to remove approximately a quarter of the thickness of the metallic plate
60
) so that a connector recess
63
is formed. In this regard, when the metallic plate
60
is a copper plate, ferric chloride is preferably used as the etching liquid. Subsequently, in FIG.
7
(
d
), the etching resist
61
is stripped off to result in the connector recess
63
in the metallic substrate
60
.
In FIG.
7
(
e
), an etching resist (photosensitive resist)
61
is again coated on the metallic substrate
60
on which the connector recess
63
has been formed, and the exposure and development are carried out while overlaying a photo-mask on the etching resist in alignment therewith to result in a pattern
64
having a central vacant space of a required size (see FIG.
8
(
b
)). Then, a second half etching is carried out (to remove an approximately quarter of a thickness of the metallic substrate
60
) in FIG.
7
(
f
) so that a mounting recess
65
is formed. Next, in FIG.
7
(
g
), the etching resist
61
is stripped off to form the connector recess
63
and the mounting recess
65
having different thicknesses from each other in a stepwise configuration. In this regard, an area and a thickness of the half etching are freely adjustable by changing the design of the central vacant space pattern in the photo-mask.
Next, in FIG.
7
(
h
), a multi-layered metallic film is formed, while coating the remainder of the metallic substrate
60
other than the connector recess
63
and the mounting recess
65
with a resist, not shown, by the electrolytic plating, vapor deposition or sputtering. Thus a carrier substrate
66
on which the mounting part metallic film
53
is formed in a stepwise configuration.
The repetition of the steps of coating the etching resist
61
onto the metallic substrate
60
and half-etching the same after being exposed and developed complicates the production process to increase the production cost. To form the first central vacant pattern
62
and the second central vacant pattern
64
of different sizes at a position aligned with each other, a highly accurate alignment is required, which causes the generation of many rejected products to lower the yield.
SUMMARY OF THE INVENTION
Accordingly, an object of the present invention is to provide a semiconductor device capable of being mass-produced at a low cost, a method for producing the same, a carrier substrate used therefor and a method for producing the same by solving the above-mentioned problems in the prior art to simplify the manufacturing process.
According to the present invention, there is provided a semiconductor device comprising: a semiconductor element having at least one signal electrode and at least one ground electrode; a mounting part metallic film having a bottom area on which the semiconductor element is mounted and a stepped area located at a periphery of the bottom area and being higher in horizontal level than the bottom area; a connector part metallic film spaced from the mounting part metallic film and arranged at a peripheral region thereof; electrical connecting means for electrically connecting the signal electrode of the semiconductor element to the connector part metallic film and connecting the ground electrode of the semiconductor element to the stepped area of the mounting part metallic film; and a resin for shielding the semiconductor element, the electrical connecting means, and at least mounting/connecting sides of the mounting part metallic film and the connector part metallic film.
At least one of the mounting part metallic film and the connector part metallic film comprises a four-layered film consisting of a gold layer, a palladium layer, a nickel layer and a palladium layer sequentially layered from a b

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