Process of making a storage capacitor for dram memory cell

Details Process of making a storage capacitor for dram memory cell Process of making a storage capacitor for dram memory cell

1996-06-11

1998-04-28

Ledynh, Bot L.

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

438254, H01L 2170

Patent

active

057443882

ABSTRACT:
A storage capacitor structural configuration for memory cell units of DRAM devices and a process for constructing the capacitor. The capacitor includes a first electrode and a second electrode that are each electrically conducting layers, and a storage dielectric that is a dielectric layer sandwiched between the two electrodes. The silicon substrate of the device has formed thereon a field oxide layer and a transistor including a gate and a pair of source/drain regions. A first dielectric layer covers the transistor and includes a contact opening over one of the source/drain regions. The first electrode includes a first electrically conducting layer formed inside the contact opening and covering the revealed surface of the source/drain region and the first dielectric layer. A second electrically conducting layer having a rugged surface is formed on the surface of the first electrically conducting layer. A number of deep grooves are formed in the second and first electrically conducting layers, forming a grid-like configuration. The storage dielectric includes a second dielectric layer covering the surface of the grid-like configuration of the second and first electrically conducting layers. The second electrode includes a third electrically conducting layer that covers the surface of the storage dielectric.

REFERENCES:
patent: 5130885 (1992-07-01), Fazan et al.
patent: 5254503 (1993-10-01), Kenney
patent: 5274258 (1993-12-01), Ahn
patent: 5447878 (1995-09-01), Park et al.
patent: 5519238 (1996-05-01), Lu

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