Process of making a dram cell arrangement

Details Process of making a dram cell arrangement Process of making a dram cell arrangement

1996-04-22

1998-10-06

Bowers, Jr., Charles L.

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

438270, H01L 218242

Patent

active

058175520

ABSTRACT:
For each storage cell, the DRAM cell arrangement has a vertical MOS transistor, the first source/drain region of which is connected to a memory node of a storage capacitor, the channel region of which is annularly enclosed by a gate electrode and the second source/drain region of which is connected to a buried bit line. The DRAM cell arrangement can be produced with a storage-cell area of 4F.sup.2 by using only two masks, F being the minimum producible structure size in the respective technology.

REFERENCES:
patent: 5307310 (1994-04-01), Narita
patent: 5362665 (1994-11-01), Lu
JP-A-01 248557 (Toshiba Corp.), 04 Oct. 1989.
Patent Abstracts of Japan. vol. 14. No. 479, (E-992) 18 Oct. 1990, & JP-A-02 198170 (Hitach Ltd.), 06 Aug. 1990.
Patent Abstracts of Japan, vol. 9, No. 140 (E-321) 14 Jun. 1985, & JP-A-60 021558 (Mitsubishi Denki K.K.), 02 Feb. 1985.
1993 Symposium on VLSI Technology, Digest of Technical Papers, vol. 3A, No. 2, May 1993, A Straight-Line-Trench Isolation and Trench-Gate Transitor (SLIT) Cell for Giga-bit DRAMs, M. Sakao et al, pp. 19-20.

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