Process of forming self-aligned silicide on source/drain region

Details Process of forming self-aligned silicide on source/drain region Process of forming self-aligned silicide on source/drain region

2000-03-10

2001-05-29

Pham, Long (Department: 2823)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S607000, C438S683000

Reexamination Certificate

active

06238989

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Technical Field
The present invention relates to semiconductor technology, and, particularly, to a process of forming self-aligned silicides on a MOS device.
2. Description of Related Art
As device dimensions approached 1 micrometer, the conventional contact structures used up to that point began to limit device performance in several ways. For example, the device contact resistance is larger when the area of the source/drain regions is reduced. A variety of contact structures have been investigated to alleviate the above problem. One is self-aligned silicides on the source/drain regions. (When these silicides are formed at the same time as the polycide structure, the approach referred to as a salicide process). The other is raised source/drain regions (formed by Si deposition onto the exposed source/drain regions).
Raised source/drain engineering using selective epitaxial Si (epi-Si) growth has become important recently. This technology not only provides more Si for better salicidation, but also prevents the consumption of substrate silicon during the salicide process. Therefore, low leakage current (resulting from no substrate consumption) can be obtained, which is especially useful for shallow junction applications. However, as shown in
FIG. 1
, when selective epi-Si
102
is used to form source/drain (S/D) regions
104
, pre-amorpharization implant (PAI) hardly reaches the substrate
100
. As a result, silicides
106
are formed only above Si-substrate
100
and is separated from the lightly doped drains (LDDs)
108
by a distance
110
. This distance
110
causes a region having high series resistance (R
s
) and low drain current (I
dsat
) between the silicides
106
and the LDDs
108
.
SUMMARY OF THE INVENTION
It is an object the present invention to provide a method of forming self-aligned silicides on source/drain regions that satisfies the need identified in the background section.
Other objects and advantages of this invention will become apparent to those of ordinary skill in the art having reference to the following specification in conjunction the drawings.
In the present invention, a method is proposed to solve the prior art issue by forming epitaxial facets on epitaxial silicon film near the gate spacers. By doing so, a light dose pre-amorphization implant (PAI) can be performed onto the substrate near the gate spacers. As TI (or Co) is sputtered on the epitaxial silicon film to form suicides, a smooth but shallow connection will be formed between the silicides and the LDDs. Therefore, a high drain current (I
dsat
) can be obtained without leakage.
To form the facets, the SiH
2
Cl
2
(dichlorsilane; DCS) concentration is reduced from normally about 150 sccm to about 50 sccm by adding the mixture of H
2
flow (about 5 slm) and HCl (about 10-50 sccm). This ratio increases the growing selectivity of epitaxial silicon on silicon (Si) substrate rather than on silicon nitride (SiN), wherein the SiN is a material of the gate spacers.
In another aspect, the present invention provides a process for forming a silicide on a source/drain region of a MOS device, wherein the MOS device has a gate spacer partially covering the source/drain region. A silicon film is formed on the source/drain region, wherein the silicon film has a portion near the gate spacer substantially thinner than the other portion of the silicon film, because of the formation of a facet on the portion of the silicon film. The silicon film is reacted with a metal film, thereby wholly consuming the portion of the silicon film near the gate spacer, and thereby partially consuming the other portion of the silicon film.
The facet inherently guides the silicide toward the spacer, and thereby prevents the lateral growth of the silicide. Because the lateral growth of the silicide is prevented, the contact area and the leakage current are both reduced.


REFERENCES:
patent: 5967794 (1999-10-01), Kodoma
patent: 5998248 (1999-12-01), Ma et al.
patent: 6025242 (2000-02-01), Ma et al.
patent: 6063675 (2000-05-01), Rodder
patent: 6127233 (2000-10-01), Rodder

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