Semiconductor device manufacturing: process – Introduction of conductivity modifying dopant into... – Ion implantation of dopant into semiconductor region
Reexamination Certificate
1997-05-30
2002-08-27
Weiss, Howard (Department: 2814)
Semiconductor device manufacturing: process
Introduction of conductivity modifying dopant into...
Ion implantation of dopant into semiconductor region
C438S621000, C438S766000
Reexamination Certificate
active
06440828
ABSTRACT:
FIELD OF THE INVENTION
This invention relates to a process of fabricating a semiconductor device and, more particularly, to a process of fabricating a semiconductor device with a low-resistive contact without a high temperature heat treatment.
DESCRIPTION OF THE RELATED ART
In order to form a low-resistivity contact with a semiconductor substrate in a contact hole, refractory metal film is deposited so as to cover the contact area of the semiconductor substrate, and the refractory metal reacts with the semiconductor through a heat-treatment so as to produce a refractory metal silicide layer. Titanium is attractive, because the titanium forms a low Schottky barrier together with any one of the p-type semiconductors and the n-type semiconductors. Moreover, the titanium easily reduces natural oxide unavoidably covering the contact area, and the silicidation smoothly proceeds.
An experiment is reported by Akihiro Sakamoto et al in “Lower Thickness Limit of Ti Film in BLK-W Contact”, Proceedings of 38th. Spring Conference of Applied Physics Society, 30p-W-7. According to the paper, a titanium film was deposited form 5 nanometers to 40 nanometers thick on a single crystal silicon substrate, and was annealed at 800 degrees centigrade for 30 seconds. Sakamoto et. al. taught that the contact resistance was drastically increased when the titanium film was equal to or less than 10 nanometers thick.
A process of forming a metal-semiconductor ohmic contact is disclosed in Japanese Patent Publication of Unexamined Application No. 4-215424. According to the Japanese Patent Publication of Unexamined Application, arsenic was ion implanted into a semiconductor layer so as to make the semiconductor layer amorphous, and titanium was deposited to 100 nanometers thick on the amorphous semiconductor layer. The titanium layer was annealed at a low temperature equal to or less than 500 degrees centigrade.
The first prior art ohmic contact disclosed in the paper encounters a problem in high contact resistance, because the ohmic contact is formed with the single crystal silicon. The high temperature annealing is another problem. The high temperature annealing causes the dopant impurity to be diffused into the silicon substrate, and destroys the impurity profile.
The impurity profile is less affected in the second prior art process, because the titanium layer is annealed at the relatively low temperature. However, the amorphous silicon layer requires the thick titanium layer of 100 nanometers thick, and the deposition consumes time and a large amount of titanium. Thus, the second prior art process encounters another problem in high production cost.
A problem inherent in the second prior art contact is a high contact resistance. The high contact resistance is derived from shortage of dopant impurity in the contact area. The dopant impurity tends to be diffused into the thick refractory metal silicide layer, and makes the dopant concentration in the contact area light. This tendency is conspicuous in a miniature contact hole of the order of 0.5 micron by 0.5 micron square or 0.5 micron in diameter.
The aspect ratio of the contact hole is getting larger and larger together with the integration density. It is impossible to properly deposit refractory metal on the bottom surface of a miniature contact hole with a large aspect ratio through sputtering. Device manufacturers try to use a chemical vapor deposition so as to perfectly grow a refractory metal layer or a refractory metal silicide layer over the surface defining the miniature contact hole with the large aspect ratio. However, the refractory metal grows differently on the contact area depending upon the conductivity type of the contact area. When the refractory metal is concurrently deposited on a heavily doped p-type contact area and a heavily doped n-type contact area, the refractory metal layer on the heavily doped p-type contact area is different in thickness from the heavily doped n-type contact area. If one of the refractory metal layers is optimized, the other refractory metal layer is so thin that the electric resistance is increased. On the other hand, if the other refractory metal layer is optimized, the refractory metal layer is too thick, and leakage current is increased.
SUMMARY OF THE INVENTION
It is therefore an important object of the present invention to provide a process of fabricating a semiconductor device through which the contact resistance of a miniature contact hole is decreased by using a low temperature heat treatment.
It is also an important object of the present invention to provide a process of fabricating a semiconductor device through which contact areas different in conductivity type are properly covered with refractory metal layers or refractory metal silicide layers.
The present inventors contemplated the problems, and investigated influences of crystal structure on the contact resistance. The present inventors formed p-type single crystal impurity regions exposed by miniature contact holes of 0.5 micron square and p-type amorphous impurity regions also exposed by miniature contact holes of 0.5 micron square. The present inventors deposited titanium on the p-type single crystal impurity regions and the p-type amorphous impurity regions, and varied the thickness of the titanium layers. The titanium layers were treated with heat at 500 degrees centigrade for 30 minutes in nitrogen ambience, and titanium silicide layers formed contacts with the p-type single crystal impurity regions and the p-type amorphous impurity regions. The present inventors measured the contact resistance, and plotted the contact resistances in FIG.
1
. Plot PL
1
represents the contact resistance of the p-type single crystal impurity regions, and plot PL
2
was indicative of the contact resistance of the p-type amorphous impurity regions.
The present inventors noticed that the contact resistance was varied between the single crystal and the amorphous silicon regions. The single crystal region required a thick titanium layer for a low resistivity contact, while the amorphous region formed a low-resistivity contact between 3 nanometers thick and 10 nanometers thick. The present inventors first concluded that the amorphous refractory metal layer between 3 nanometers and 10 nanometers thick was desirable for a low-resistivity contact.
The present inventors further investigated growing technologies, and found that a chemical vapor deposition was available for refractory metal deposited on an amorphous dopant impurity region exposed by a miniature contact hole with a large aspect ratio. A contact region was changed to amorphous by using an ion-implantation. Boron/boron difluoride (BF
2
) or phosphorous/arsenic was desirable for the ion-implantation. If TiCl
4
was reduced in the chemical vapor deposition, titanium was deposited at a certain temperature not higher than 600 degrees centigrade.
In accordance with one aspect of the present invention, there is provided a process of fabricating a semiconductor device on a semiconductor substrate, comprising: a) preparing a semiconductor layer; b) forming an insulating layer over the semiconductor layer; c) forming an opening in the insulating layer so that the semiconductor layer is exposed to the opening; d) making the semiconductor layer exposed to the opening amorphous; e) depositing a refractory metal layer from 3 nanometers to 10 nanometers thick on the semiconductor layer; and f) treating the refractory metal layer with heat so as to convert the refractory metal layer to a refractory metal silicide layer.
In accordance with another aspect of the present invention, there is provided a process of fabricating a semiconductor device, comprising the steps of: a) preparing a semiconductor layer; b) forming an insulating layer having an opening where the semiconductor layer is exposed; c) making the semiconductor layer exposed to the opening amorphous; and d) depositing a refractory metal layer by using a chemical vapor deposition so as to grow a refractory metal silicide on the semiconductor layer.
REFEREN
Sato Shunichiro
Shinmura Toshiki
Taguwa Tetsuya
Urabe Koji
Yamada Yoshiaki
NEC Corporation
Pizarro-Crespo Marcos D.
Sughrue & Mion, PLLC
Weiss Howard
LandOfFree
Process of fabricating semiconductor device having... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Process of fabricating semiconductor device having..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Process of fabricating semiconductor device having... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2970346