Process of controlling plural test access ports

Details Process of controlling plural test access ports Process of controlling plural test access ports

2001-10-16

2004-03-23

Tu, Christine T. (Department: 2133)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital logic testing

C714S798000

Reexamination Certificate

active

06711707

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to an improved method and system for testing multiple intellectual property cores contained within an integrated circuit, each core including a standard IEEE-1149.1 compliant test access port (TAP). A core is a predefined subcircuit function, which can be incorporated into the design of an integrated circuit. Some example core functions include but are not limited to: digital signal processors, microcontrollers, microprocessors, and memories. The present invention achieves the above mentioned testing without having to change or modify the standard TAPs of each core. Using the present invention, the TAPs of each core are made selectable such that they can be connected to the integrated circuit pins to enable direct communication between the integrated circuit pins and selected core TAPs.
2. Brief Description of the Prior Art
The IEEE-1149.1 standard, known as JTAG, is a standardized test system developed for testing chips on a board. A trend in the semiconductor industry is for popular chip functions to evolve into intellectual property core circuit functions to allow them to be provided for reuse in the design of larger, more complex integrated circuits. As semiconductor chips evolve into intellectual property cores, the JTAG test system may remain as an integral part of the core. Thus cores will contain the JTAG test system, which facilitates the testing of the cores in chips similar to the way JTAG facilitates the testing of chips on boards.
The present invention assumes plural cores of an integrated circuit each contain a standard IEEE 1149.1 TAP interface comprising a test data input (TDI), test data output (TDO), test mode select (TMS), test clock (TCK), and a test reset (TRST). According to the present invention, as will be described in detail below, a TAP Linking Module is located between the 1149.1 interfaces of the core TAPs and a corresponding 1149.1 test pin interface of the integrated circuit. The TAP Linking Module provides selectivity between the integrated circuit's 1149.1 test pin interface and one or more of the core TAP 1149.1 test interfaces. Core testing takes place by connecting a tester of standard type to the integrated circuit test pins, communicating information via the test pins to the TAP Linking Module to select one or more of the core TAPs to be connected the test pins, and thereafter applying test patterns to the one or more cores via the connection formed by the TAP Linking Module.
It is important to note that some cores use the TAP not only for testing but also for emulation, debug, code development, and system level fault diagnosis. Therefore the present invention not only provides for selective core testing, but also for selective core emulation, debug, code development, and fault diagnosis operations.
A prior art paper entitled “An IEEE 1149.1 Test Access Architecture For ICs With Embedded Cores” by Whetsel was published in the 1997 International Test Conference proceedings, pages 69-78, and is incorporated herein by reference. This paper provides detail on the problems associated with accessing TAPs of cores embedded in integrated circuits. Further, the paper provides a solution to this problem by describing how the design of standard TAPs of cores may be modified to enable them to operate in co-operation with a TAP Linking Module, such that one or more of the modified core TAPs may be selectively accessed for test and emulation via the TAP Linking Module.
Whetsel U.S. Pat. Nos. 5,056,093 and 5,054,024 describe a system for switching between TAPs by use of a Device Select Module (DSM). This approach locates the DSM between the tester and plurality of TAPs to allow the 1149.1 instruction and data scans to pass through the DSM and the currently selected TAPs. 1149.1 instruction and data scans are used to enable the DSM to switch between the TAPs. In this approach the DSM is scanned during every 1149.1 instruction and data scan operation to the selected TAPs. The TAP linking module of the present invention is scanned during every 1149.1 instruction scan operation to the selected TAPs, but not during 1149.1 data scan operations to the selected TAPs. 1149.1 data scan operations to the TAP linking module occurs only when no TAPs are selected for scanning. Thus 1149.1 data scans to the TAP linking module occur separate from 1149.1 data scan to the TAPs. The difference therefore between the DSM and TAP linking module is that the DSM is scanned along with the selected TAPs during 1149.1 data scans, while 1149.1 data scans to the TAP linking module occur separate from 1149.1 data scans to the TAPs.
The TAP linking module of the present invention provides the benefits described for the TAP linking module in the Whetsel paper, but without having to modify the design of the standard TAP. The importance of not having to modify the standard TAP can be seen in pre-existing (legacy) core designs which are not modifiable. For example, non-modifiable legacy cores with TAPs may be provided by intellectual property core vendors. Since the cores are not modifiable, their TAPs cannot be modified for use with the TAP Lining Module described in the Whetsel paper. The present invention provides a method of achieving the same advantages stated in the Whetsel paper but without having to modify the TAP design.
As described in the Whetsel paper, existing core TAP access techniques either; (1) provide extra test interface pins (TDI, TDO, TMS, TCK, TRST) on the integrated circuit for each TAP, or (2) string all TAPs together serially via their TDI and TDO signals and in parallel via their TMS, TCK, and TRST signals and connect the TAP string to one set of test interface pins on the integrated circuit. When extra test pins are used, each TAP has its own test interface. However, this approach requires the integrated circuit to have more test pins and the tester to have more scan interface resources. When core TAPs are connected in a string, the speed at which the string of TAPs may be serially operated (i.e. scanned) is dependant upon each TAP's maximum TCK frequency rate. For example, a string of three TAPs may exist where the first TAP can operate at a 40 Mhz maximum TCK rate, the second TAP can operate at a 10 Mhz maximum TCK rate, and the third TAP can operate at a 50 Mhz maximum TCK rate. When scanning the string of TAPs, the TCK frequency rate of the string cannot exceed the maximum TCK rate of the second TAP. Therefore scan operations through the TAP string is limited to 10 Mhz, even though the first and third TAPs can operate at 40 and 50 Mhz, respectively. Also, stringing TAPs together does not allow one TAP to be placed in an 1149.1 RunBist self-test mode while the other TAPs are being scanned.
The present invention, as described in detail below, provides a TAP Linking Module design which uses instruction augmentation to achieve a TAP selection system supporting selectable access of non-modifiable TAPs contained within legacy cores.
SUMMARY OF THE INVENTION
In accordance with the present invention, selection and testing of multiple TAP'ed cores within a large integrated circuit can be performed without adding test interface pins beyond those specified by the IEEE 1149.1 standard, and without modifying the TAP design of the cores. This is accomplished by a novel design of the Tap Linking Module, referred to hereafter as TLM, which eliminates the need to redesign core TAPs.
Briefly, the present invention enables an IEEE 1149.1 test pin interface on an integrated circuit to access any number of standard TAPs within an integrated circuit by providing a TLM that is operable to switch the TAPs to the test pins in response to 1149.1 scan operations. No design modifications are required on TAPs used with the present invention.
It is an object of the present invention to provide the following features.
(1) Provide a TLM architecture for integrated circuits which operates to enable and disable 1149.1 scan access to TAPs without having to modify the design of TAPs. Hence, the inventio

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