Process improvements in self-aligned polysilicon MOSFET technolo

Details Process improvements in self-aligned polysilicon MOSFET technolo Process improvements in self-aligned polysilicon MOSFET technolo

1997-05-05

1999-07-27

Booth, Richard A

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

438786, 438303, H01L 218247

Patent

active

059306270

ABSTRACT:
Silicon enriched silicon oxynitride is used in applications both as an independent etch stop and as a cap layer and sidewall component over polysilicon gate electrodes in order to prevent insulator thinning and shorts caused by a mis-aligned contact mask. In one embodiment a silicon enriched silicon oxynitride layer is placed over a polysilicon gate with conventional sidewalls and insulative cap. In another embodiment the insulative cap and the sidewalls are formed of a silicon enriched silicon oxinitride. Etching of contact openings in the subsequently deposited insulative layer is suppressed by the silicon enriched silicon oxynitride if it is engaged because of a mis-aligned contact mask. In another embodiment a polysilicon stack edge of a memory device is protected by a conformal silicon oxynitride layer during etching of a self-aligned-source (SAS) region. These embodiments are accomplished with minimal and virtually negligible increase in process complexity or cost.

REFERENCES:
patent: 4871689 (1989-10-01), Bergami et al.
patent: 4901133 (1990-02-01), Curran et al.
patent: 5120671 (1992-06-01), Tang et al.
patent: 5208472 (1993-05-01), Su et al.
patent: 5286667 (1994-02-01), Lin et al.
patent: 5492853 (1996-02-01), Jeng et al.
patent: 5534455 (1996-07-01), Liu
patent: 5643833 (1997-07-01), Tsukamoto
patent: 5736442 (1998-04-01), Mori
S. Wolf, "Silicon Processing for the VLSI Era" vol. 2, Lattice Press, Sunset Beach, CA (1990), p143.
Wolf et al, "Silicon Processing for the VLSI Era" vol. 1, Lattice Press (1986), p195.
Ghandhi, "VLSI Fabrication Principles" 2nd Edition, A Wiley-Interscience Publication, p484-5, Date Unknown.

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