Process for wafer peripheral edge defect reduction

Details Process for wafer peripheral edge defect reduction Process for wafer peripheral edge defect reduction

1997-01-13

1999-03-09

Breneman, R. Bruce

Etching a substrate: processes

Nongaseous phase etching of substrate

Projecting etchant against a moving substrate or controlling...

216 49, 216 95, 216 97, 438748, H01L 21302

Patent

active

058795774

ABSTRACT:
A method is described for selectively etching photoresist on a semiconductor substrate having one or more layers of a spin on glass, including an edge bead that was formed when the glass was originally applied. First the wafer is coated with a layer of unexposed, undeveloped negative photoresist. Then, while spinning the wafer, a vertical jet of photoresist EBR solvent is directed to a point just inside the edge so that photoresist gets removed from an annular area extending inwards from the perimeter. The edge bead is then removed using a liquid etchant and integrated circuit processing can now proceed, making use of the unexposed, undeveloped layer of photoresist in the usual way; that is, exposing it through a mask and then developing and baking it before using it as an etch mask. The method is general and may be used in other situations where selective removal of photoresist along the periphery is required and where the remaining resist is to be used for other purposes.

REFERENCES:
patent: 4510176 (1985-04-01), Cuthbert et al.
patent: 4732785 (1988-03-01), Brewer
patent: 5168021 (1992-12-01), Arai et al.
patent: 5328871 (1994-07-01), Tanigawa et al.
patent: 5425846 (1995-06-01), Koze et al.
patent: 5609995 (1997-03-01), Akram et al.
patent: 5773083 (1998-06-01), Fischer et al.
patent: 5779928 (1998-07-01), Yamashita et al.
patent: 5783097 (1998-07-01), Lo et al.
"Novel edge bead process--by channeling UV light through cable to expose resist at edge of spinning wafer after post-exposure baking before development" Research Disclosure #331,028, Nov. 1991.

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