Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Utility Patent
1999-09-23
2001-01-02
Bowers, Charles (Department: 2813)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S289000, C438S270000, C438S272000
Utility Patent
active
06169000
ABSTRACT:
BACKGROUND OF THE INVENTION AND RELATED ART STATEMENT
The present invention relates to a process for the production of a semiconductor substrate having a silicon-on-insulator structure and a process for the production of a semiconductor device for which the above process for production of a semiconductor substrate having a silicon-on-insulator structure is applied.
The SOI (Silicon-On-Insulator) method of forming a semiconductor device in a single crystal silicon layer formed on an insulating layer composed of, for example, SiO
2
is excellent in a-ray durability and a latch-up characteristic and is also suitable for suppressing short channel effect. It is an essential problem how to form a thin single crystal silicon layer (called SOI layer) on the insulating layer.
For forming an SOI layer, for example, a SIMOX (Separation by IMplanted OXygen) method is known. In the SIMOX method, a silicon semiconductor substrate is ion-implanted with a high dosage (for example, 1.8×10
18
cm
−2
to 2.0×10
18
cm
−2
) of an oxygen ion at high acceleration energy (for example, 180 to 200 keV) and then annealed at a high temperature to form a buried insulating layer composed of SiO
2
inside the silicon semiconductor substrate. A portion above the buried insulating layer is left as a silicon semiconductor layer (SOI) layer, and a semiconductor device is formed in the SOI layer.
As other method for forming an SOI layer, there is known a so-called substrate-bonding method. The substrate-bonding method will be outlined with reference to
FIGS. 15A
,
15
B,
16
A,
16
B and
17
hereinafter.
First, a trench portion
12
is formed in a semiconductor substrate
10
by lithography and etching processes (see FIG.
15
A). Then, an approximately 0.6 &mgr;m thick insulating layer
20
composed of SiO
2
is formed on the entire surface by a known CVD method, to fill up the trench portion
12
with the insulating layer
20
. Further, an approximately 5 &mgr;m thick polycrystalline silicon (polysilicon) layer
21
is formed on the entire surface by a known CVD method, and the surface of the polycrystalline silicon layer
21
is planarized. This state is shown in FIG.
15
B.
Thereafter, the silicon semiconductor substrate
10
and a supporting substrate
30
are bonded to each other through the insulating layer
20
and further through the polycrystalline silicon layer
21
(see FIG.
16
A). The above bonding is carried out, for example, under a condition of an oxygen gas atmosphere at 1100° C. for 30 minutes.
Then, the silicon semiconductor substrate
10
is ground and polished from its rear surface. Specifically, first, the silicon semiconductor substrate
10
is mechanically ground with diamond grinding grains from its rear surface until the silicon semiconductor substrate
10
comes to be several &mgr;m thick from the bottom portion
12
A of the trench portion
12
so that no grinding damage is caused to remain in the SOI layer (see FIG.
16
B). Then, the silicon semiconductor substrate
10
is selectively polished by a chemical/mechanical polishing method (CMP method) until the bottom
12
A of the trench portion
12
is exposed. The insulating layer
20
filled in the trench portion
12
works as a polishing-stop layer, and a semiconductor layer
10
A which is a remaining portion of the silicon semiconductor substrate
10
is left as an SOI layer (see FIG.
17
). The trench portion
12
formed in the silicon semiconductor substrate
10
is in a state where it is filled with the insulating layer
20
, and it works for a device isolation region.
In the SIMOX method, since a silicon semiconductor substrate is ion-implanted with a high dosage of an ion at high acceleration energy, the crystal defect density in the silicon semiconductor substrate is approximately 100 times as large as the crystal defect density in a single crystal silicon semiconductor substrate produced by a general Czochralski method. When a semiconductor device is formed in the semiconductor layer
10
A having such a high crystal defect density, the problem is that all the semiconductor devices that can be obtained show poor performances. Further, there is caused a “pipe” phenomenon, an inherent phenomenon of the SIMOX method, that particles adhering the surface of the silicon semiconductor substrate prevent the ion-implantation, and a current path to the silicon semiconductor substrate is formed. As a result, the semiconductor device is liable to cause a failure in performances and a decrease in reliability.
When the semiconductor layer
10
A which is a remaining portion of the semiconductor substrate is formed by polishing the semiconductor substrate from its rear surface in the substrate-bonding method, not only it is difficult to control the thickness of the semiconductor layer
10
A, but also a variation in the thickness of the semiconductor layer
10
A is liable to take place. Further, an in-plane variation in one silicon semiconductor substrate is also liable to take place. Particular, when the semiconductor layer
10
A surrounded by the trench portions
12
formed in the silicon semiconductor substrate
10
has a large area, a so-called dishing phenomenon is liable to take place in which the surface of the semiconductor layer
10
A is polished to form a concave shape (see FIG.
18
).
The present Applicant proposed methods for overcoming the above problems of the SIMOX method or substrate-bonding methods by filing Japanese patent applications which have been laid-open as JP-A-7-226433 and JP-A-8-279605. In the methods disclosed in the above Japanese Laid-open Patent Publications, an SOI layer is formed by a combination of the SIMOX method and the substrate-bonding method. That is, a buried polishing-stop layer is formed inside a silicon semiconductor substrate by the SIMOX method, an insulating layer is formed on the silicon semiconductor substrate, then, the silicon semiconductor substrate and a supporting substrate are bonded to each other through the insulating layer, and then, the silicon semiconductor substrate is ground and polished from its rear surface until the buried polishing-stop layer is reached. In the methods disclosed in JP-A-7-226433 and JP-A-8-279605, the silicon semiconductor substrate is polished from its rear surface until the buried polishing-stop layer is reached, then, the buried polishing-stop layer is removed, and then, SOI layer is further polished to form a thin SOI layer.
In recent years, one method is attracting attention, in which the SOI layer is thickness-decreased to 100 nm or less and source/drain regions of a MOS type transistor are formed along the entire thickness of the SOI layer. Since the capacitance of the source/drain regions decreases, particularly, the transistor can be operated at a high speed at a low voltage of a power source, and the above method is expected to materialize a low power consumption.
As explained above, for producing a semiconductor device which permits high-speed operation at a low voltage of a power source and has high reliability, it is essential to form an SOI layer which has a low crystal defect density and has a small thickness.
In the methods disclosed in the above Japanese Laid-open Patent Publications, the thickness of a formed SOI layer is as large as 100 nm to 200 nm, the dosage of an ion implanted for forming a buried polishing-stop layer by the SIMOX method is as high as 1×10
17
cm
−2
to 1×10
18
cm
−2
, and the formed buried insulating layer comes to have a thickness of approximately 0.1 &mgr;m to 0.4 &mgr;m. Due to the above high dosage of the ion-implantation, the silicon semiconductor substrate where the SOI layer is to be formed has a high crystal defect density. It is therefore essentially required to decrease the crystal defects by polishing the silicon semiconductor substrate from its rear surface until the buried polishing-stop layer is reached, removing the buried polishing-stop layer and then further polishing the SOI layer to decrease the SOI layer in thickness. However, the step of further pol
Bowers Charles
Kananen Ronald P.
Rader Fishman & Grauer
Schillinger Laura
Sony Corporation
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