Process for the production of an integrated CMOS circuit

Details Process for the production of an integrated CMOS circuit Process for the production of an integrated CMOS circuit

1996-09-24

1999-03-16

Trinh, Michael

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

438229, 438232, 438291, 438296, 438297, 438301, H01L 218238

Patent

active

058829644

ABSTRACT:
In order to produce an integrated CMOS circuit, a dielectric layer and a silicon layer are applied to a substrate. During the formation of insulation structurers which insulate neighboring active regions in the substrate, the silicon layer is structured in such a way that it has separate sub-regions which are subsequently doped differently. By full-surface deposition of an electrically conductive layer and common structuring of the electrically conductive layer and the structured silicon layer differently doped gate electrodes and a metallization plane, by which the gate electrodes are electrically connected, are formed. Division of the silicon layer before doping prevents lateral dopant diffusion.

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patent: 4847213 (1989-07-01), Pfiester
patent: 5407840 (1995-04-01), Manoliu et al.
patent: 5438214 (1995-08-01), Egawa et al.
International Journal of High Speed Electronics and Systems, vol. 5, No. 2, 1994, pp. 135-143, D. Yu et al.
International Journal of High Speed Electronics and Systems, vol. 5, No. 2 (1994), World Scientific Publishing Company, D.C.H. Yu et al, New Robust n.sup.+ /p.sup.+ Dual-Gate CMOS Technology Optimized for Low Power Operation, pp. 135-143.
IEDM (1988), IBM Research Division, T.J. Watson Research Center, Yorktown Hts., N.Y., Doping of N.sup.30 And P.sup.+ Polysilicon in a Dual-Gate CMOS Process, C.Y. Wong et al, pp. 238-241.
IEDM (1985), (Invited Paper), Motorola, Inc., Austin, TX., Process and Device Considerations for Micron and Submicron CMOS Technology, L.C. Parrillo, pp. 398-402.

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